HD6432670 Hitachi, HD6432670 Datasheet - Page 658

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

[1] Setting of compare match flags
[2] Counter clear specification
[3] Pin output
13.6.2
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A’s for channel
0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
13.7
13.7.1
There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are
shown in table 13.3. Each interrupt source is set as enabled or disabled by the corresponding
interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the
interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB
interrupts.
Rev. 2.0, 04/02, page 612 of 906
The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match
event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter
clear by the TMRI0 pin has also been set.
The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
16-bit compare match conditions.
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
lower 8-bit compare match conditions.
Compare Match Count Mode
Interrupt Sources and DTC Activation
Interrupts