HD6432670 Hitachi, HD6432670 Datasheet - Page 829

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

3. The target value is set in bits STC1 and STC0, and a transition is made to software standby
4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
6. After the set transition time has elapsed, this LSI resumes operation using the target
When STCS = 1, this LSI operates using the new multiplication factor immediately after bits
STC1 and STC0 are rewritten.
21.4
The frequency divider divides the PLL output clock to generate a 1/2, 1/4, 1/8, 1/16, or 1/32 clock.
21.5
21.5.1
1. The following points should be noted since the frequency of
2. All the on-chip peripheral modules operate on the
3. Note that the frequency of
21.5.2
Since various characteristics related to the resonator are closely linked to the user’s board design,
thorough evaluation is necessary on the user’s part, using the oscillator connection examples
shown in this section as a guide. As the parameters for the oscillation circuit will depend on the
floating capacitance of the resonator and the user board, the parameters should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the oscillator pin.
mode.
setting in STS3 to STS0.
multiplication factor.
setting of SCKCR and PLLCR.
Select the clock division ratio that is within the operation guaranteed range of clock cycle time
tcyc shown in the AC timing of Electrical Characteristics. In other words, the range of
be specified from 8 MHz (min) to 33 MHz (max); outside of this range must be prevented.
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software
Standby Mode in section 22.2.3, Software Standby Mode, for details.
the external bus cycle with the write-data-buffer function or the EXDMAC.
Usage Notes
Frequency Divider
Notes on Clock Pulse Generator
Notes on Resonator
will be changed when setting SCKCR or PLLCR while executing
. Therefore, note that the time processing
Rev. 2.0, 04/02, page 783 of 906
changes according to the
must