HD6432670 Hitachi, HD6432670 Datasheet - Page 352

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when
Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
Rev. 2.0, 04/02, page 306 of 906
Address bus
ø
Bus release
Figure 7.18 Example of Short Address Mode Transfer
DMA
read
output is enabled,
DMA
write
Bus release
DMA
read
DMA
write
output goes low in the transfer end cycle.
Bus release
DMA
read
Last transfer
cycle
DMA
write
DMA
dead
Bus
release

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