HD6432670 Hitachi, HD6432670 Datasheet - Page 364

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Figure 7.31 shows an example of single address mode transfer activated by the
level.
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes,
sampling is performed again, and this operation is repeated until the transfer ends.
Rev. 2.0, 04/02, page 318 of 906
Figure 7.31 Example of
Address bus
DMA control
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Channel
pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
Acceptance after transfer enabling; the
and the request is held.
(As in [1], the
ø
pin low level is sampled while acceptance by means of the
Idle
[1]
Request
Bus release
Minimum of
pin low level is sampled on the rising edge of ø, and the request is held.)
2 cycles
[2]
Pin Low Level Activated Single Address Mode Transfer
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
pin low level is sampled on the rising edge of ø,
[4]
Request
Bus release
Minimum of
2 cycles
[5]
[6]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
pin low level
pin is
[7]
pin low
release
Bus