HD6432670 Hitachi, HD6432670 Datasheet - Page 374

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

4. Bus release cycle
5. CBR refresh cycle
Figure 7.41 shows an example in which a low level is not output from the
above.
If the last transfer cycle is an external address cycle, a low level is output at the
synchronization with the bus cycle.
However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the
CBR refresh and the last transfer cycle may be executed consecutively,
this case for the refresh cycle.
7.7.5
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the
Rev. 2.0, 04/02, page 328 of 906
switches to [2].
switches to [1].
pin falling edge detection is performed in synchronization with DMAC internal operations.
Internal write signal
Internal read signal
Activation by Falling Edge on
External address
Figure 7.41 Example in Which Low Level is Not Output at
Internal address
,
ø
External write by CPU, etc.
Pin
DMA
read
Not output
DMA
write
may also go low in
pin in case 2
pin, and
Pin
pin, and
pin in