HD6432670 Hitachi, HD6432670 Datasheet - Page 13

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.8
6.9
6.10 Write Data Buffer Function .......................................................................................... 245
6.11 Bus Release ................................................................................................................. 246
6.12 Bus Arbitration ............................................................................................................251
6.13 Bus Controller Operation in Reset ................................................................................ 253
6.14 Usage Notes................................................................................................................. 253
Section 7 DMA Controller (DMAC) ..............................................................255
7.1
7.2
7.3
7.4
6.7.12 Burst Operation ............................................................................................... 210
6.7.13 Refresh Control ............................................................................................... 214
6.7.14 Mode Register Setting of Synchronous DRAM ................................................ 219
6.7.15 DMAC and EXDMAC Single Address Transfer Mode and
Burst ROM Interface.................................................................................................... 226
6.8.1
6.8.2
6.8.3
Idle Cycle .................................................................................................................... 229
6.9.1
6.9.2
6.11.1 Operation ........................................................................................................ 246
6.11.2 Pin States in External Bus Released State......................................................... 248
6.11.3 Transition Timing............................................................................................ 249
6.12.1 Operation ........................................................................................................ 251
6.12.2 Bus Transfer Timing........................................................................................ 251
6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode ............ 253
6.14.2 External Bus Release Function and Software Standby ...................................... 253
6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing .............. 253
6.14.4
6.14.5 Notes on Usage of the Synchronous DRAM..................................................... 254
Features ....................................................................................................................... 255
Input/Output Pins ......................................................................................................... 257
Register Descriptions ................................................................................................... 257
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Activation Sources ....................................................................................................... 282
7.4.1
7.4.2
Synchronous DRAM Interface ......................................................................... 221
Basic Timing ................................................................................................... 226
Wait Control.................................................................................................... 228
Write Access ................................................................................................... 228
Operation ........................................................................................................ 229
Pin States in Idle Cycle .................................................................................... 245
Memory Address Registers (MARA and MARB)............................................. 258
I/O Address Registers (IOARA and IOARB) ................................................... 259
Execute Transfer Count Registers (ETCRA and ETCRB)................................. 259
DMA Control Registers (DMACRA and DMACRB) ....................................... 261
DMA Band Control Registers H and L (DMABCRH and DMABCRL) ............ 268
DMA Write Enable Register (DMAWER) ....................................................... 279
DMA Terminal Control Register (DMATCR) .................................................. 281
Activation by Internal Interrupt Request........................................................... 282
Activation by External Request ........................................................................ 283
Output Timing ................................................................................... 254
Rev. 2.0, 04/02, page xi of xliv