HD6432670 Hitachi, HD6432670 Datasheet - Page 12

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.4
6.5
6.6
6.7
Rev. 2.0, 04/02, page x of xliv
6.3.9
6.3.10 Refresh Control Register (REFCR) .................................................................. 147
6.3.11 Refresh Timer Counter (RTCNT) .................................................................... 150
6.3.12 Refresh Time Constant Register (RTCOR)....................................................... 150
Bus Control ................................................................................................................. 150
6.4.1
6.4.2
6.4.3
6.4.4
Basic Bus Interface ...................................................................................................... 156
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
DRAM Interface .......................................................................................................... 170
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
6.6.10 Byte Access Control ........................................................................................ 182
6.6.11 Burst Operation ............................................................................................... 183
6.6.12 Refresh Control ............................................................................................... 187
6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface.... 192
Synchronous DRAM Interface ..................................................................................... 195
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
6.7.9
6.7.10 Bus Cycle Control in Write Cycle .................................................................... 207
6.7.11 Byte Access Control ........................................................................................ 208
DRAM Access Control Register (DRACCR) ................................................... 143
Area Division .................................................................................................. 150
Bus Specifications ........................................................................................... 152
Memory Interfaces .......................................................................................... 153
Chip Select Signals.......................................................................................... 155
Data Size and Data Alignment ......................................................................... 156
Valid Strobes................................................................................................... 158
Basic Operation Timing................................................................................... 158
Wait Control ................................................................................................... 166
Read Strobe (
Extension of Chip Select (
Setting DRAM Space ...................................................................................... 170
Address Multiplexing ...................................................................................... 171
Data Bus ......................................................................................................... 172
Pins Used for DRAM Interface ........................................................................ 173
Basic Timing................................................................................................... 174
Column Address Output Cycle Control ............................................................ 175
Row Address Output State Control .................................................................. 176
Precharge State Control ................................................................................... 178
Wait Control ................................................................................................... 179
Setting Continuous Synchronous DRAM Space ............................................... 195
Address Multiplexing ...................................................................................... 196
Data Bus ......................................................................................................... 197
Pins Used for Synchronous DRAM Interface ................................................... 197
Synchronous DRAM Clock ............................................................................. 199
Basic Operation Timing................................................................................... 199
CAS Latency Control ...................................................................................... 201
Row Address Output State Control .................................................................. 203
Precharge State Count ..................................................................................... 205
) Timing................................................................................ 168
) Assertion Period ............................................... 169