HD6432670 Hitachi, HD6432670 Datasheet - Page 414

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Figure 8.21 Example of Block Transfer Mode Transfer Activated by
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
8.4.10
Single Address Mode (Read): Figure 8.22 shows an example of transfer when
enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-
state access space to an external device.
Rev. 2.0, 04/02, page 368 of 906
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of dead cycle.
ø
Address bus
DMA control
Channel
Acceptance after transfer enabling;
(As in [1],
pin sampling is performed in each cycle starting at the next rise of ø after the end of the
EXDMAC Bus Cycles (Single Address Mode)
Idle
[1]
Minimum 3 cycles
Request
Bus release
pin low level is sampled at rise of ø, and request is held.)
[2]
Read
Request clearance period
[3]
Transfer source
DMA read
One block transfer
Write
DMA write
destination
pin while acceptance via the
Transfer
pin low level is sampled at rise of ø, and request is held.
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
Read
Request clearance period
[6]
Transfer source
DMA read
One block transfer
Write
DMA write
destination
Transfer
pin is possible,
Idle
Acceptance
resumed
Pin Low Level
pin low level
[7]
Bus release
output is