HD6432670 Hitachi, HD6432670 Datasheet - Page 220

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.6.5
Figure 6.21 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
output cycle) state, and the T
When DRAM space is accessed, the 5' signal is output as the 2( signal for DRAM. When
connecting DRAM provided with an EDO page mode, the 2( signal should be connected to the
( 2( ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the 2( signal for DRAM
space to be output from a dedicated 2( pin. In this case, the 2( signal for DRAM space is output
Rev. 2.0, 04/02, page 174 of 906
Read
Write
Note: n = 2 to 5
Basic Timing
ø
Address bus
Data bus
Data bus
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)
(
(
(
(
,
(
)
)
)
)
)
c1
and two T
T
p
Row address
c2
(column address output cycle) states.
High
High
p
(precharge cycle) state, one T
T
r
T
c1
Column address
T
c2
r
(row address