HD6432670 Hitachi, HD6432670 Datasheet - Page 596

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the
setting procedure for cascaded operation.
Examples of Cascaded Operation: Figure 11.18 illustrates the operation when counting upon
TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been
designated as input capture registers, and the TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Rev. 2.0, 04/02, page 550 of 906
TCNT_1
clock
TCNT_1
TCNT_2
clock
TCNT_2
TIOCA1,
TIOCA2
TGRA_1
TGRA_2
<Cascaded operation>
H'FFFF
H'03A1
Cascaded operation
Figure 11.17 Cascaded Operation Setting Procedure
Set cascading
Start count
Figure 11.18 Example of Cascaded Operation (1)
[1]
[2]
H'0000
[1]
[2]
Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
H'03A2
H'03A2
H'0000
H'0001