HD6432670 Hitachi, HD6432670 Datasheet - Page 291
HD6432670
Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432670.pdf
(953 pages)
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6.9.2
Table 6.12 shows the pin states in an idle cycle.
Table 6.12 Pin States in Idle Cycle
Notes: 1. Remains low in DRAM space RAS down mode.
6.10
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.
Figure 6.83 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external write or DMA single address mode transfer continues for two states
or longer, and there is an internal access next, an external write only is executed in the first state,
but from the next state onward an internal access (on-chip memory or internal I/O register
read/write) is executed in parallel with the external write rather than waiting until it ends.
Pins
A23 to A0
D15 to D0
&6Q
8&$6
$6
5'
(
+:5
'$&.Q
('$&.Q
2(
)
(n = 7 to 0)
,
,
/:5
/&$6
2. Remains low in a DRAM space refresh cycle.
(n = 1, 0)
(n = 3 to 0)
Pin States in Idle Cycle
Write Data Buffer Function
Pin State
Contents of following bus cycle
High impedance
High*
High*
High
High
High
High
High
High
1,
2
*
2
Rev. 2.0, 04/02, page 245 of 906
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