UPD78F1146AGB-GAH-AX

Manufacturer Part NumberUPD78F1146AGB-GAH-AX
DescriptionMCU 16BIT 78K0R/KX3 64-LQFP
ManufacturerRenesas Electronics America
Series78K0R/Kx3
UPD78F1146AGB-GAH-AX datasheet
 


Specifications of UPD78F1146AGB-GAH-AX

Core Processor78K/0RCore Size16-Bit
Speed20MHzConnectivity3-Wire SIO, I²C, LIN, UART/USART
PeripheralsDMA, LVD, POR, PWM, WDTNumber Of I /o50
Program Memory Size256KB (256K x 8)Program Memory TypeFLASH
Ram Size12K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case*
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Old Company Name in Catalogs and Other Documents
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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st
April 1
, 2010
Renesas Electronics Corporation

UPD78F1146AGB-GAH-AX Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    User’s Manual 78K0R/KE3 16-bit Single-Chip Microcontrollers μ PD78F1142, 78F1142A, 78F1142A(A) μ PD78F1143, 78F1143A, 78F1143A(A) μ PD78F1144, 78F1144A, 78F1144A(A) μ PD78F1145, 78F1145A, 78F1145A(A) μ PD78F1146, 78F1146A, 78F1146A(A) Document No. U17854EJ9V0UD00 (9th edition) Date Published September 2009 NS 2006 Printed in Japan ...

  • Page 4

    User’s Manual U17854EJ9V0UD ...

  • Page 5

    NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...

  • Page 6

    Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. EEPROM is a trademark of NEC Electronics Corporation. SuperFlash is a registered ...

  • Page 7

    Readers This manual is intended for user engineers who wish to understand the functions of the 78K0R/KE3 and design and develop application systems and programs for these devices. The target products are as follows. • Conventional-specification products of the 78K0R/KE3: ...

  • Page 8

    How to interpret the register format: → For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the RA78K0R, and is defined as an sfr variable using the #pragma sfr directive ...

  • Page 9

    Documents Related to Flash Memory Programming PG-FP4 Flash Memory Programmer User’s Manual PG-FP5 Flash Memory Programmer Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. ...

  • Page 10

    CHAPTER 1 OUTLINE ............................................................................................................................ 17 1.1 Differences Between Conventional-Specification Products ( Specification Products ( 1.2 Features......................................................................................................................................... 18 1.3 Applications .................................................................................................................................. 19 1.4 Ordering Information.................................................................................................................... 19 1.5 Pin Configuration (Top View) ...................................................................................................... 21 1.6 78K0R/Kx3 Microcontroller Lineup............................................................................................. 24 1.7 Block Diagram ...

  • Page 11

    Control registers................................................................................................................................63 3.2.2 General-purpose registers ................................................................................................................65 3.2.3 ES and CS registers .........................................................................................................................67 3.2.4 Special function registers (SFRs)......................................................................................................68 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)............................74 3.3 Instruction Address Addressing ................................................................................................ 79 3.3.1 Relative addressing ..........................................................................................................................79 3.3.2 ...

  • Page 12

    System Clock Oscillator ............................................................................................................ 156 5.4.1 X1 oscillator.....................................................................................................................................156 5.4.2 XT1 oscillator ..................................................................................................................................156 5.4.3 Internal high-speed oscillator ..........................................................................................................159 5.4.4 Internal low-speed oscillator............................................................................................................159 5.4.5 Prescaler .........................................................................................................................................159 5.5 Clock Generator Operation ....................................................................................................... 160 5.6 Controlling Clock........................................................................................................................ 164 5.6.1 Example of controlling high-speed ...

  • Page 13

    CHAPTER 7 REAL-TIME COUNTER .................................................................................................. 261 7.1 Functions of Real-Time Counter............................................................................................... 261 7.2 Configuration of Real-Time Counter ........................................................................................ 261 7.3 Registers Controlling Real-Time Counter ............................................................................... 263 7.4 Real-Time Counter Operation ................................................................................................... 278 7.4.1 Starting operation of real-time counter ............................................................................................278 7.4.2 ...

  • Page 14

    Cautions for A/D Converter ..................................................................................................... 328 CHAPTER 11 SERIAL ARRAY UNIT.................................................................................................. 333 11.1 Functions of Serial Array Unit................................................................................................. 333 11.1.1 3-wire serial I/O (CSI00, CSI10) ....................................................................................................333 11.1.2 UART (UART0, UART1, UART3) ..................................................................................................334 2 11.1.3 Simplified I C (IIC10) .....................................................................................................................335 ...

  • Page 15

    Transfer direction specification .....................................................................................................493 12.5.4 Transfer clock setting method .......................................................................................................494 12.5.5 Acknowledge (ACK) ......................................................................................................................495 12.5.6 Stop condition ...............................................................................................................................497 12.5.7 Wait...............................................................................................................................................498 12.5.8 Canceling wait...............................................................................................................................500 12.5.9 Interrupt request (INTIIC0) generation timing and wait control......................................................501 12.5.10 Address match detection method................................................................................................502 12.5.11 Error ...

  • Page 16

    Software interrupt request acknowledgment .................................................................................593 15.4.3 Multiple interrupt servicing.............................................................................................................594 15.4.4 Interrupt request hold ....................................................................................................................597 CHAPTER 16 KEY INTERRUPT FUNCTION ..................................................................................... 598 16.1 Functions of Key Interrupt ...................................................................................................... 598 16.2 Configuration of Key Interrupt ................................................................................................ 598 16.3 Register Controlling Key ...

  • Page 17

    Setting of Option Byte ............................................................................................................. 659 CHAPTER 23 FLASH MEMORY.......................................................................................................... 660 23.1 Writing with Flash Memory Programmer............................................................................... 660 23.2 Programming Environment..................................................................................................... 663 23.3 Communication Mode.............................................................................................................. 663 23.4 Connection of Pins on Board.................................................................................................. 664 23.4.1 FLMD0 pin ....................................................................................................................................664 23.4.2 TOOL0 ...

  • Page 18

    CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) .................................. 705 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) ................................... 758 CHAPTER 29 PACKAGE DRAWINGS ................................................................................................. 810 CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS........................................................... 815 APPENDIX A DEVELOPMENT TOOLS............................................................................................... 817 A.1 Software Package ...................................................................................................................... 820 A.2 ...

  • Page 19

    Differences Between Conventional-Specification Products ( Specification Products ( This manual describes the functions of the 78K0R/KE3 microcontroller products with conventional specifications μ ( PD78F114x) and expanded specifications ( The differences between the conventional-specification products ( μ products ( PD78F114xA) ...

  • Page 20

    Features Minimum instruction execution time can be changed from high speed (0.05 speed system clock) to ultra low-speed (61 General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks) ROM, RAM capacities Item Part ...

  • Page 21

    Applications Home appliances • Laser printer motors • Clothes washers • Air conditioners • Refrigerators Home audio systems Digital cameras, digital video cameras 1.4 Ordering Information • Flash memory version (lead-free products) Part Number μ PD78F1142GK-GAJ-AX μ PD78F1142AGK-GAJ-AX μ ...

  • Page 22

    Part Number μ PD78F1142AGA-HAB-AX μ PD78F1143AGA-HAB-AX μ PD78F1144AGA-HAB-AX μ PD78F1145AGA-HAB-AX μ PD78F1146AGA-HAB-AX μ PD78F1142AF1-AN1-A μ PD78F1143AF1-AN1-A μ PD78F1144AF1-AN1-A μ PD78F1145AF1-AN1-A μ PD78F1146AF1-AN1-A μ PD78F1142AF1-BA4-A μ PD78F1143AF1-BA4-A μ PD78F1144AF1-BA4-A μ PD78F1145AF1-BA4-A μ PD78F1146AF1-BA4 ...

  • Page 23

    Pin Configuration (Top View) • 64-pin plastic LQFP (12 × 12) • 64-pin plastic LQFP (fine pitch) (10 × 10) • 64-pin plastic TQFP (fine pitch) (7 × 7) P120/INTP0/EXLVI P43 P42/TI04/TO04 P41/TOOL1 P40/TOOL0 RESET P124/XT2 P123/XT1 FLMD0 P122/X2/EXCLK ...

  • Page 24

    FBGA (5 × 5) Note • 64-pin plastic FBGA (6 × 6) Top View Index mark Pin No. Pin Name Pin No. A1 P30/INTP3/RTC1HZ C1 A2 P05/TI05/TO05 C2 A3 P06/TI06/TO06 C3 A4 ...

  • Page 25

    Pin Identification ANI0-ANI7: Analog input AV : Analog reference voltage REF AV : Analog ground Power supply for port Ground for port SS EXCLK: External clock input (main system clock) EXLVI: External potential input ...

  • Page 26

    Microcontroller Lineup ROM RAM 78K0R/KE3 64 Pins − 512 − 384 μ 256 PD78F1146 μ PD78F1146A μ 192 PD78F1145 μ PD78F1145A μ 128 ...

  • Page 27

    Block Diagram TIMER ARRAY UNIT (8ch) TI00/P00 ch0 TO00/P01 ch1 TI01/TO01/P16 ch2 TI02/TO02/P17 TI03/TO03/P31 ch3 TI04/TO04/P42 ch4 TI05/TO05/P05 ch5 ch6 TI06/TO06/P06 RxD3/P14 (LINSEL) ch7 LOW-SPEED INTERNAL OSCILLATOR WINDOW WATCHDOG TIMER RTCDIV/RTCCL/P15 REALTIME COUNTER RTC1HZ/P30 SERIAL ARRAY UNIT0 (4ch) RxD0/P11 ...

  • Page 28

    Outline of Functions μ Item μ Internal Flash memory 64 KB memory (self-programming supported) RAM 4 KB Memory space 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock ...

  • Page 29

    Item PD78F1142, μ PD78F1142A • UART supporting LIN-bus: Serial interface • UART/CSI: • UART/CSI/simplified I • bits × 16 bits = 32 bits Multiplier DMA controller 2 channels Vectored interrupt Internal 25 sources External 13 Key interrupt ...

  • Page 30

    Pin Function List There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply AV REF CHAPTER 2 PIN FUNCTIONS , EV , and ...

  • Page 31

    Port functions (1/2) Function Name I/O P00 I/O Port 0. 7-bit I/O port. P01 Input of P03 and P04 can be set to TTL input buffer. P02 Output of P02 to P04 can be set to N-ch open-drain output ...

  • Page 32

    Port functions (2/2) Function Name I/O P120 I/O Port 12. 1-bit I/O port and 4-bit input port. P121 Input For only P120, use of an on-chip pull-up resistor can be specified P122 by a software setting. P123 P124 P130 ...

  • Page 33

    Non-port functions (1/2) Function Name I/O ANI0 to ANI7 Input A/D converter analog input EXLVI Input Potential input for external low-voltage detection INTP0 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both ...

  • Page 34

    Non-port functions (2/2) Function Name I/O TI00 Input External count clock input to 16-bit timer 00 TI01 External count clock input to 16-bit timer 01 TI02 External count clock input to 16-bit timer 02 TI03 External count clock input ...

  • Page 35

    Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, and clock I/O. Input to the P03 and P04 ...

  • Page 36

    SCL10 This is a serial clock I/O pin of serial interface for simplified I Caution To use P02/SO10/TxD1 and P04/SCK10/SCL10 as general-purpose ports, set serial communication operation setting register 02 (SCR02) to the default status (0087H). In addition, clear ...

  • Page 37

    TO01, TO02 These are the timer output pins of 16-bit timers 01 and 02. (j) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) ...

  • Page 38

    TI03 This is a pin for inputting an external count clock/capture trigger to 16-bit timer 03. (c) TO03 This is a timer output pin from 16-bit timer 03. (d) RTC1HZ This is a real-time counter correction clock (1 Hz) ...

  • Page 39

    In normal operation mode and when on-chip debugging is enabled (OCDENSET = option byte (000C3H) => Connect this pin to EV the pin before reset release. (c) When on-chip debug function is used write ...

  • Page 40

    Port mode P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be ...

  • Page 41

    P130 (port 13) P130 functions as a 1-bit output port. Remark When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before the device is reset, the output signal of P130 ...

  • Page 42

    AV SS This is the ground potential pin of A/D converter, P20 to P27. Even when the A/D converter is not used, always use this pin with the same potential as EV 2.2.14 RESET This is the active-low system ...

  • Page 43

    FLMD0 This is a pin for setting flash memory programming mode. Perform either of the following processing. (a) In normal operation mode It is recommended to leave this pin open during normal operation. The FLMD0 pin must always be ...

  • Page 44

    Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins. Table 2-3. Connection of Unused Pins (1/2) Pin Name I/O Circuit Type P00/TI00 8-R ...

  • Page 45

    Table 2-3 Connection of Unused Pins (2/2) Pin Name I/O Circuit Type Note P121/X1 37-B Note P122/X2/EXCLK Note P123/XT1 Note P124/XT2 P130 3-C P140/PCLBUZ0/INTP6 8-R P141/PCLBUZ1/INTP7 − AV REF − FLMD0 2-W RESET 2 − REGC Note Use ...

  • Page 46

    Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 2 P-ch N- Schmitt-triggered input with hysteresis characteristics Type 3-C EV Data EV 44 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type ...

  • Page 47

    Type 11-G AV Data Output disable AV P-ch Comparator + _ N-ch Series resistor string voltage AV SS Input enable Type 13-P Data Output N-ch disable EV SS Input enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List ...

  • Page 48

    Memory Space Products in the 78K0R/KE3 can access memory space. Figures 3-1 to 3-5 show the memory maps. Figure 3-1. Memory Map ( Special function register (SFR ...

  • Page 49

    Figure 3-2. Memory Map (μPD78F1143, 78F1143A Special function register (SFR) 256 bytes General-purpose register 32 bytes ...

  • Page 50

    Figure 3-3. Memory Map (μPD78F1144, 78F1144A Special function register (SFR) 256 bytes General-purpose register 32 bytes ...

  • Page 51

    Figure 3-4. Memory Map ( Special function register (SFR) 256 bytes General-purpose register 32 bytes ...

  • Page 52

    Figure 3-5. Memory Map ( Special function register (SFR) 256 bytes General-purpose register 32 bytes ...

  • Page 53

    Remark The flash memory is divided into blocks (one block = 2 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory ...

  • Page 54

    Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Address Value Number 00000H to 007FFH 00H 10000H to 107FFH ...

  • Page 55

    Internal program memory space The internal program memory space stores the program and table data. 78K0R/KE3 products incorporate internal ROM (flash memory), as shown below. Part Number μ PD78F1142, 78F1142A μ PD78F1143, 78F1143A μ PD78F1144, 78F1144A μ PD78F1145, 78F1145A ...

  • Page 56

    Vector Table Address Interrupt Source 00000H RESET input, POC, LVI, WDT, TRAP 00004H INTWDTI 00006H INTLVI 00008H INTP0 0000AH INTP1 0000CH INTP2 0000EH INTP3 00010H INTP4 00012H INTP5 00014H INTST3 00016H INTSR3 00018H INTSRE3 0001AH INTDMA0 0001CH INTDMA1 0001EH INTST0/INTCSI00 ...

  • Page 57

    Mirror area μ The PD78F1142 and 78F1142A mirror the data flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. μ The PD78F1143, 78F1143A, 78F1144, 78F1144A, 78F1145, 78F1145A, 78F1146, 78F1146A mirror the data flash area of 00000H to 0FFFFH ...

  • Page 58

    Processor mode control register (PMC) This register selects the flash memory space for mirroring to area from F0000H to FFFFFH. PMC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to ...

  • Page 59

    Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not ...

  • Page 60

    Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...

  • Page 61

    Figure 3-8. Correspondence Between Data Memory and Addressing ( Special function register (SFR 256 bytes ...

  • Page 62

    Figure 3-9. Correspondence Between Data Memory and Addressing ( Special function register (SFR 256 bytes ...

  • Page 63

    Figure 3-10. Correspondence Between Data Memory and Addressing ( Special function register (SFR 256 bytes ...

  • Page 64

    Figure 3-11. Correspondence Between Data Memory and Addressing ( Special function register (SFR 256 bytes ...

  • Page 65

    Processor Registers The 78K0R/KE3 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and ...

  • Page 66

    Auxiliary carry flag (AC) If the operation result has a carry from bit borrow at bit 3, this flag is set (1 reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) ...

  • Page 67

    Figure 3-15. Data to Be Saved to Stack Memory PUSH rp instruction SP←SP−2 ↑ Register pair lower SP−2 ↑ SP−1 Register pair higher ↑ → SP CALL, CALLT instructions (4-byte stack) SP←SP−4 ↑ PC7 to PC0 SP−4 ↑ SP−3 PC15 ...

  • Page 68

    Figure 3-16. Configuration of General-Purpose Registers FFEFFH Register bank 0 FFEF8H Register bank 1 FFEF0H Register bank 2 FFEE8H Register bank 3 FFEE0H FFEFFH Register bank 0 FFEF8H Register bank 1 FFEF0H Register bank 2 FFEE8H Register bank 3 FFEE0H ...

  • Page 69

    ES and CS registers The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is ...

  • Page 70

    Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable ...

  • Page 71

    Address Special Function Register (SFR) Name FFF00H Port register 0 FFF01H Port register 1 FFF02H Port register 2 FFF03H Port register 3 FFF04H Port register 4 FFF05H Port register 5 FFF06H Port register 6 FFF07H Port register 7 FFF0CH Port ...

  • Page 72

    Address Special Function Register (SFR) Name FFF30H A/D converter mode register FFF31H Analog input channel specification register FFF37H Key return mode register FFF38H External interrupt rising edge enable register 0 FFF39H External interrupt falling edge enable register 0 FFF3AH External ...

  • Page 73

    Address Special Function Register (SFR) Name FFF90H Sub-count register FFF91H FFF92H Second count register FFF93H Minute count register FFF94H Hour count register FFF95H Week count register FFF96H Day count register FFF97H Month count register FFF98H Year count register FFF99H Watch ...

  • Page 74

    Address Special Function Register (SFR) Name FFFB0H DMA SFR address register 0 FFFB1H DMA SFR address register 1 FFFB2H DMA RAM address register 0L FFFB3H DMA RAM address register 0H FFFB4H DMA RAM address register 1L FFFB5H DMA RAM address ...

  • Page 75

    Address Special Function Register (SFR) Name FFFEEH Priority specification flag register 11L FFFEFH Priority specification flag register 11H FFFF0H Multiplication input data register A FFFF1H FFFF2H Multiplication input data register B FFFF3H FFFF4H Higher multiplication result storage register FFFF5H FFFF6H ...

  • Page 76

    Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the ...

  • Page 77

    Table 3-6. Extended SFR (2nd SFR) List (1/4) Address Special Function Register (SFR) Name F0017H A/D port configuration register F0030H Pull-up resistor option register 0 F0031H Pull-up resistor option register 1 F0033H Pull-up resistor option register 3 F0034H Pull-up resistor ...

  • Page 78

    Table 3-6. Extended SFR (2nd SFR) List (2/4) Address Special Function Register (SFR) Name F0118H Serial communication operation setting register 00 F0119H F011AH Serial communication operation setting register 01 F011BH F011CH Serial communication operation setting register 02 F011DH F011EH Serial ...

  • Page 79

    Table 3-6. Extended SFR (2nd SFR) List (3/4) Address Special Function Register (SFR) Name F0164H Serial channel stop register 1 F0165H F0166H Serial clock select register 1 F0167H F0168H Serial output register 1 F0169H F016AH Serial output enable register 1 ...

  • Page 80

    Table 3-6. Extended SFR (2nd SFR) List (4/4) Address Special Function Register (SFR) Name F01A0H Timer status register 00 F01A1H F01A2H Timer status register 01 F01A3H F01A4H Timer status register 02 F01A5H F01A6H Timer status register 03 F01A7H F01A8H Timer ...

  • Page 81

    Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the ...

  • Page 82

    Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address ...

  • Page 83

    Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies ...

  • Page 84

    Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] ...

  • Page 85

    Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is ...

  • Page 86

    Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier SADDR Label, FFE20H ...

  • Page 87

    SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier SFR SFR name SFRP ...

  • Page 88

    Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier − [DE], [HL] (only the space from F0000H ...

  • Page 89

    Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used ...

  • Page 90

    Figure 3-32. Example of [HL + byte], [DE + byte] OP code byte Figure 3-33. Example of word[B], word[C] OP code Low Addr. High Addr. OP code Low Addr. High Addr. 88 CHAPTER 3 CPU ARCHITECTURE rp (HL/DE) Target memory ...

  • Page 91

    CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of ES:[HL + byte], ES:[DE + byte (HL/DE) OP code byte Figure 3-36. Example of ES:word[B], ES:word[ (B/C) OP code Low Addr. High Addr. Figure 3-37. Example of ES:word[BC] ...

  • Page 92

    Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word ...

  • Page 93

    Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of ...

  • Page 94

    Port Functions There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply AV REF 78K0R/KE3 products are provided with the ports shown in Figure ...

  • Page 95

    Function Name I/O P00 I/O Port 0. 7-bit I/O port. P01 Input of P03 and P04 can be set to TTL input buffer. P02 Output of P02 to P04 can be set to N-ch open-drain output P03 (V tolerance). DD ...

  • Page 96

    Function Name I/O P60 I/O Port 6. 4-bit I/O port. P61 Output of P60 to P63 can be set to N-ch open-drain output (6 P62 V tolerance). P63 Input/output can be specified in 1-bit units. P70 to P73 I/O Port ...

  • Page 97

    Port Configuration Ports include the following hardware. Item Control registers Port mode registers (PM0 to PM7, PM12, PM14) Port registers (P0 to P7, P12 to P14) Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, PU14) Port ...

  • Page 98

    Port 0 Port 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 ...

  • Page 99

    CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 WR PU PU0 PU01 RD WR PORT P0 Output latch (P01 PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode ...

  • Page 100

    WR PU PU0 PU02 RD WR PORT P0 Output latch (P02) WR POM POM0 POM02 WR PM PM0 PM02 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port output mode ...

  • Page 101

    CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P03 and P04 WR PIM PIM0 PIM03, PIM04 WR PU PU0 PU03, PU04 Alternate function RD WR PORT P0 Output latch (P03, P04) WR POM POM0 POM03, POM04 WR PM PM0 ...

  • Page 102

    Figure 4-6. Block Diagram of P05 and P06 WR PU PU0 PU05, PU06 Alternate function RD WR PORT P0 Output latch (P05, P06 PM0 PM05, PM06 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 ...

  • Page 103

    Port 1 Port 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 ...

  • Page 104

    WR PU PU1 PU10 Alternate function RD WR PORT P1 Output latch (P10 PM1 PM10 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal ...

  • Page 105

    CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P11 and P14 WR PU PU1 PU11, PU14 Alternate function RD WR PORT P1 Output latch (P11, P14 PM1 PM11, PM14 P1: Port register 1 PU1: Pull-up resistor option ...

  • Page 106

    Figure 4-9. Block Diagram of P12 and P13 WR PU PU1 PU12, PU13 RD WR PORT P1 Output latch (P12, P13 PM1 PM12, PM13 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port ...

  • Page 107

    CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P15 WR PU PU1 PU15 RD WR PORT P1 Output latch (P15 PM1 PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode ...

  • Page 108

    Figure 4-11. Block Diagram of P16 and P17 WR PU PU1 PU16, PU17 Alternate function RD WR PORT P1 Output latch (P16, P17 PM1 PM16, PM17 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 ...

  • Page 109

    Port 2 Port 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be ...

  • Page 110

    Figure 4-12. Block Diagram of P20 to P27 RD WR PORT P2 Output latch (P20 to P27 PM2 PM20 to PM27 P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR××: Write signal 108 CHAPTER ...

  • Page 111

    Port 3 Port 2-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 and P31 ...

  • Page 112

    Port 4 Port 4-bit I/O port with a output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P43 ...

  • Page 113

    CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P40 WR PU PU4 PU40 Alternate function RD WR PORT P4 Output latch (P40 PM4 PM40 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: ...

  • Page 114

    WR PU PU4 PU41 RD WR PORT P4 Output latch (P41 PM4 PM41 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal 112 CHAPTER ...

  • Page 115

    CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P42 WR PU PU4 PU42 Alternate function RD WR PORT P4 Output latch (P42 PM4 PM42 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: ...

  • Page 116

    WR PU PU4 PU43 RD WR PORT P4 Output latch (P43 PM4 PM43 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal 114 CHAPTER 4 PORT ...

  • Page 117

    Port 5 Port 6-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P55 ...

  • Page 118

    Figure 4-19. Block Diagram of P52 to P55 WR PU PU5 PU52 to PU55 RD WR PORT P5 Output latch (P52 to P55 PM5 PM52 to PM55 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: ...

  • Page 119

    Port 6 Port 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The output of the P60 ...

  • Page 120

    Figure 4-21. Block Diagram of P62 and P63 RD WR PORT Output latch (P62, P63 PM6 PM62, PM63 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WR××: Write signal 118 CHAPTER 4 PORT FUNCTIONS ...

  • Page 121

    Port 7 Port 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 ...

  • Page 122

    Port 12 P120 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, ...

  • Page 123

    CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P121 and P122 Clock generator RD RD CMC: Clock operation mode control register RD: Read signal User’s Manual U17854EJ9V0UD CMC OSCSEL CMC EXCLK, OSCSEL P122/X2/EXCLK P121/X1 121 ...

  • Page 124

    Figure 4-25. Block Diagram of P123 and P124 RD RD CMC: Clock operation mode control register RD: Read signal 122 CHAPTER 4 PORT FUNCTIONS Clock generator CMC OSCSELS CMC OSCSELS User’s Manual U17854EJ9V0UD P124/XT2 P123/XT1 ...

  • Page 125

    Port 13 P130 is a 1-bit output-only port with an output latch. Figure 4-26 shows block diagrams of port 13 PORT Output latch (P130) P13: Port register 13 RD: Read signal WR××: Write signal Remark When reset ...

  • Page 126

    Port 14 Port 2-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 and P141 ...

  • Page 127

    CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of P140 and P141 WR PU PU14 PU140, PU141 Alternate function RD WR PORT P14 Output latch (P140, P141 PM14 PM140, PM141 Alternate function P14: Port register 14 PU14: Pull-up ...

  • Page 128

    Registers Controlling Port Function Port functions are controlled by the following six types of registers. • Port mode registers (PM0 to PM7, PM12, PM14) • Port registers (P0 to P7, P12 to P14) • Pull-up resistor option registers (PU0, ...

  • Page 129

    Figure 4-28. Format of Port Mode Register Symbol PM0 1 PM06 PM05 PM1 PM17 PM16 PM15 PM2 PM27 PM26 PM25 PM3 PM4 PM5 1 1 PM55 PM6 PM7 ...

  • Page 130

    Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is ...

  • Page 131

    Symbol P06 P05 P1 P17 P16 P15 P2 P27 P26 P25 P55 P77 P76 P75 P12 ...

  • Page 132

    Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30, P31, P40 to P43, P50 to P55, P70 to P77, P120, ...

  • Page 133

    Port input mode registers (PIM0) This register sets the input buffer of P03 or P04 in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. This register can be ...

  • Page 134

    A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation ...

  • Page 135

    Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, ...

  • Page 136

    Connecting to external device with different power potential (2 When parts of ports 0 operate with V 2 power supply voltage are possible. Regarding inputs, CMOS/TTL switching is possible on a bit-by-bit ...

  • Page 137

    Setting procedure when using I/O pins of simplified IIC10 functions <1> After reset release, the port mode is the input mode (Hi-Z). <2> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used). In case ...

  • Page 138

    Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5. Table 4-5. Settings of Port ...

  • Page 139

    Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Function Name Note Note P20 to P27 ANI0 to ANI7 P30 RTC1HZ INTP3 P31 TI03 TO03 INTP4 P40 TOOL0 P41 TOOL1 P42 TI04 ...

  • Page 140

    Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject ...

  • Page 141

    Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This ...

  • Page 142

    Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Clock operation mode control register (CMC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) ...

  • Page 143

    Clock operation mode Clock operation status control register control register (CMC) (CSC) AMPH EXCLK OSCSEL MSTOP STOP High-speed system clock oscillator f MX X1/P121 Crystal/ceramic f X oscillation X2/EXCLK Internal /P122 External input f EX high-speed f clock IH oscillator ...

  • Page 144

    Remark clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency High-speed system clock frequency Main system clock frequency MAIN <R> f ...

  • Page 145

    Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/P124 pins, and to select a gain of the oscillator. CMC can be written only once by an ...

  • Page 146

    Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock, and subsystem clock (except the internal low-speed oscillation clock). CSC can be set by a 1-bit ...

  • Page 147

    Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Clock • CLS = 0 and MCS = 0 X1 clock • CLS = 1 External main system (CPU and peripheral hardware clocks operate with a clock clock other than ...

  • Page 148

    Figure 5-4. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST ...

  • Page 149

    Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits ...

  • Page 150

    Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol 7 6 OSTS 0 0 OSTS2 OSTS1 Cautions ...

  • Page 151

    System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a division ratio. CKC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 09H. ...

  • Page 152

    Cautions 1. Be sure to set bit The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to ...

  • Page 153

    Peripheral enable registers 0 (PER0) These registers are used to enable or disable use of each peripheral hardware macro. Clock supply to the hardware that is not used is also stopped decrease the power consumption and ...

  • Page 154

    Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2) SAU1EN 0 Stops input clock supply. • SFR used by the serial array unit 1 cannot be written. • The serial array unit the reset status. 1 ...

  • Page 155

    Operation speed mode control register (OSMC) This register is used to control the step-up circuit of the flash memory for high-speed operation. If the microcontroller operates at a low speed with a system clock of 10 MHz or less, ...

  • Page 156

    Internal high-speed oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the internal high-speed oscillator. With self-measurement of the internal high-speed oscillator frequency via a subsystem clock using a crystal resonator, a timer using high-accuracy ...

  • Page 157

    Figure 5-9. Format of Internal High-Speed Oscillator Trimming Register (HIOTRM) Address: F00F2H After reset: 10H Symbol 7 6 HIOTRM 0 0 TTRM4 TTRM3 ...

  • Page 158

    System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input ...

  • Page 159

    Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as ...

  • Page 160

    Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, ...

  • Page 161

    Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0R/KE3 (8 MHz (TYP.)). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). After a reset release, the internal high-speed oscillator ...

  • Page 162

    Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). • Main system clock f MAIN • High-speed system clock clock ...

  • Page 163

    Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1)) Power supply 1.8 V voltage ( 1.59 V (TYP.) 0.5 V/ms (MIN.) 0 ...

  • Page 164

    Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 ...

  • Page 165

    Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. 2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation ...

  • Page 166

    Controlling Clock 5.6.1 Example of controlling high-speed system clock The following two types of high-speed system clocks are available. • X1 clock: Crystal/ceramic resonator is connected to the X1 and X2 pins. • External main system clock: External clock ...

  • Page 167

    Example of setting procedure when using the external main system clock <1> Setting P121/X1 and P122/X2/EXCLK pins (CMC register) EXCLK OSCSEL 1 1 Remarks 1. ×: don’t care 2. For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3 ...

  • Page 168

    If some peripheral hardware macros are not used, supply of the input clock to each hardware macro can be stopped. (PER0 register) RTCEN 0 xxxEN 0 Stops input clock supply. 1 Supplies input clock. Caution Be sure to clear ...

  • Page 169

    To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (CKC register) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system ...

  • Page 170

    Setting the internal high-speed oscillation clock as the source clock of the CPU/peripheral hardware clock and setting the division ratio of the set clock (CKC register) MCM0 MDIV2 Caution If switching the ...

  • Page 171

    Stopping the internal high-speed oscillation clock (CSC register) When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped. Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP ...

  • Page 172

    Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillation (See 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.) Note The setting of <1> is not necessary when ...

  • Page 173

    Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Used only as the watchdog timer clock. The internal low-speed oscillator automatically starts oscillation after a reset release, and the ...

  • Page 174

    CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15. CPU Clock Status Transition Diagram Internal high-speed oscillation: Operating Internal high-speed oscillation: X1 oscillation/EXCLK input: Selectable by CPU Selectable by ...

  • Page 175

    Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status ...

  • Page 176

    Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) → ...

  • Page 177

    Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) → ...

  • Page 178

    Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4) <R> (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) → (C) ...

  • Page 179

    Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. CPU Clock Before Change After Change Internal high- X1 clock speed oscillation ...

  • Page 180

    CPU Clock Before Change After Change Subsystem Internal high- Oscillation of internal high-speed oscillator Note clock speed oscillation and selection of internal high-speed clock oscillation clock as main system clock • HIOSTOP = 0, MCS = 0 X1 clock Stabilization ...

  • Page 181

    Time required for switchover of CPU clock and main system clock By setting bits and 6 (MDIV0 to MDIV2, MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between ...

  • Page 182

    Table 5-9. Maximum Number of Clocks Required in Type 3 Set Value Before Switchover CSS CLK MAINC CLK SUB <R> Remarks 1. f :Internal high-speed oscillation clock frequency IH f :High-speed ...

  • Page 183

    The timer array unit has eight 16-bit timers per unit. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer. Single-operation ...

  • Page 184

    Functions of each channel when it operates with another channel Combination-operation functions are those functions that are attained by using the master channel (mostly the reference timer that controls cycles) and the slave channels (timers that operate following the ...

  • Page 185

    Configuration of Timer Array Unit The timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Timer/counter Timer counter register 0n (TCR0n) Register Timer data register 0n (TDR0n) Timer input TI00 to TI06 pins, ...

  • Page 186

    Figure 6-1. Block Diagram of Timer Array Unit Timer clock select register 0 (TPS0) Peripheral enable register 0 PRS013 PRS012PRS011 PRS010 TAU0EN (PER0 CLK Selector TI00/P00 Channel 0 CK00 MCK CK01 f /4 SUB Edge detection TIS01 Slave/master ...

  • Page 187

    Timer/counter register 0n (TCR0n) TCR0n is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is ...

  • Page 188

    The TCR0n register read value differs as follows according to operation mode changes and the operating status. Table 6-2. TCR0n Register Read Value in Various Operation Modes Operation Mode Count Mode Operation mode change after reset Interval timer Count down ...

  • Page 189

    Timer data register 0n (TDR0n) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MD0n3 ...

  • Page 190

    Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Timer clock select register 0 (TPS0) • Timer mode register 0n (TMR0n) • Timer status register 0n (TSR0n) ...

  • Page 191

    Peripheral enable register 0 (PER0) PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. ...

  • Page 192

    Timer clock select register 0 (TPS0) TPS0 is a 16-bit register that is used to select two types of operation clocks (CK00, CK01) that are commonly supplied to each channel. CK01 is selected by bits ...

  • Page 193

    Timer mode register 0n (TMR0n) TMR0n sets an operation mode of channel used to select an operation clock (MCK), a count clock, whether the timer operates as the master or a slave, a start trigger and ...

  • Page 194

    Figure 6-6. Format of Timer Mode Register 0n (TMR0n) (2/3) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) Symbol TMR0n CKS 0 0 CCS 0n 0n STS STS STS 0n2 0n1 0n0 Only ...

  • Page 195

    Figure 6-6. Format of Timer Mode Register 0n (TMR0n) (3/3) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) Symbol TMR0n CKS 0 0 CCS 0n3 0n2 0n1 0n0 0 0 ...

  • Page 196

    Timer status register 0n (TSR0n) TSR0n indicates the overflow status of the counter of channel n. TSR0n is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to MD0n1 = 110B). ...

  • Page 197

    Timer channel enable status register 0 (TE0) TE0 is used to enable or stop the timer operation of each channel. When a bit of timer channel start register 0 (TS0) is set to 1, the corresponding bit of this ...

  • Page 198

    Timer channel start register 0 (TS0) TS0 is a trigger register that is used to clear a timer counter (TCR0n) and start the counting operation of each channel. When a bit (TS0n) of this register is set to 1, ...

  • Page 199

    CHAPTER 6 TIMER ARRAY UNIT Table 6-4. Operations from Count Operation Enabled State to TCR0n Count Start (2/2) Timer operation mode • One-count mode • Capture & one-count mode (a) Start timing in interval timer mode <1> Writing 1 to ...

  • Page 200

    Start timing in event counter mode <1> While TE0n is set to 0, TCR0n holds the initial value. <2> Writing 1 to TS0n sets 1 to TE0n. <3> As soon as 1 has been written to TS0n and 1 ...