UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 865

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C.2 Revision History of Preceding Editions
4th edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
Edition
Change of status indication of
development”
1.1 Feature
• Addition of single-power supply flash memory security function
• Addition of flash shield window function to self-programming function
Changes of Figure 3-1 Memory Map (
Map (
Addition of 3.1.1(4) On-chip debug security ID setting area
Addition of Caution to 3.1.3 Internal data memory space
Addition of Caution to 3.2.4 Special function registers (SFRs)
Change of Note 1 in Table 3-5 SFR List
Change of BCD adjust result register in Table 3-5 SFR List
Addition of Caution to 3.2.5 Extended special function registers (2nd SFRs: 2nd
Special Function Registers)
Addition of Caution to Figure 5-7 Format of Peripheral Enable Register 0 (PER0)
Addition of Note 4 to 5.3 (7) Operation speed mode control register (OSMC)
Change of description of 5.3 (8) Internal high-speed oscillator trimming register
(HIOTRM)
Addition of time until CPU operation start in Figure 5-13 Clock Generator
Operation When Power Supply Voltage Is Turned On (When LVI Default Start
Function Stopped Is Set (Option Byte: LVIOFF = 1))
Change of Figure 5-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0))
Addition of Caution to 5.6.1 (3) <3>
Addition of Caution 2 to 6.3 (1) Peripheral enable register 0 (PER0)
Change of Figure 6-6 Format of Timer Mode Register 0n (TMR0n)
Addition of description to 6.3 (4) Timer status register 0n (TSR0n)
Addition of Table 6-3 OVF Bit Operation and Set/Clear Conditions in Each
Operation Mode
Addition of Table 6-4 Operations from Count Operation Enabled State to TCR0n
Count Start, and (a) through (e)
Addition of description to 6.3 (11) Timer output level register 0 (TOL0)
Change of description of 6.3 (12) Timer output mode register 0 (TOM0)
Change of Figure 6-20 Format of Timer Output Mode Register 0 (TOM0) and
Remark
Change of description to Figure 6-21 Format of Input Switch Control Register
(ISC)
Addition of 6.4 Channel Output (TO0n pin) Control
Addition of 6.5 Channel Input (TI0n Pin) Control
μ
PD78F1146)
APPENDIX C REVISION HISTORY
μ
PD78F1142 and
User’s Manual U17854EJ9V0UD
Description
μ
PD78F1142) through Figure 3-5 Memory
μ
PD78F1143 to “under
Throughout
CHAPTER 1 OUTLINE
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
Chapter
(1/15)
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