UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 192

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

190
Address: F01B6H, F01B7H
(2) Timer clock select register 0 (TPS0)
Symbol
TPS0
TPS0 is a 16-bit register that is used to select two types of operation clocks (CK00, CK01) that are commonly
supplied to each channel. CK01 is selected by bits 7 to 4 of TPS0, and CK00 is selected by bits 3 to 0.
Rewriting of TPS0 during timer operation is possible only in the following cases.
Rewriting of PRS000 to PRS003 bits: Possible only when all the channels set to CKS0n = 0 are in the
Rewriting of PRS010 to PRS013 bits: Possible only when all the channels set to CKS0n = 1 are in the
TPS0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TPS0 can be set with an 8-bit memory manipulation instruction with TPS0L.
Reset signal generation clears this register to 0000H.
Note
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. f
PRS
0m3
When changing the clock selected for f
value), stop the timer array unit (TT0 = 00FFH).
15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
2. m = 0, 1 n = 0 to 7
PRS
0m2
14
CLK
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
: CPU/peripheral hardware clock frequency
PRS
0m1
Figure 6-5. Format of Timer Clock Select Register 0 (TPS0)
After reset: 0000H
13
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
PRS
0m0
12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
11
0
CHAPTER 6 TIMER ARRAY UNIT
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/2
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
operation stopped state (TE0n = 0)
operation stopped state (TE0n = 0)
User’s Manual U17854EJ9V0UD
R/W
10
0
9
0
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.62 kHz
7.81 kHz
3.91 kHz
1.95 kHz
976 Hz
488 Hz
244 Hz
122 Hz
61 Hz
CLK
f
CLK
= 2 MHz
(by changing the system clock control register (CKC)
Selection of operation clock (CK0m)
8
0
PRS
013
7
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.2 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.76 kHz
4.88 kHz
2.44 kHz
1.22 kHz
610 Hz
305 Hz
153 Hz
f
PRS
CLK
012
6
= 5 MHz
PRS
011
5
PRS
010
5 MHz
2.5 MHz
625 kHz
312.5 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.76 kHz
4.88 kHz
2.44 kHz
1.22 kHz
610 Hz
10 MHz
1.25 MHz
156.2 kHz
305 Hz
4
f
CLK
= 10 MHz
PRS
003
Note
3
PRS
002
2
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.2 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.76 kHz
4.88 kHz
2.44 kHz
1.22 kHz
610 Hz
f
CLK
PRS
001
= 20 MHz
1
PRS
000
0