UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 602

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.1 Standby Function and Configuration
17.1.1 Standby function
(1) HALT mode
(2) STOP mode
set are held. The I/O port output latches and output buffer statuses are also held.
17.1.2 Registers controlling standby function
600
The standby function reduces the operating current of the system, and the following two modes are available.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the
high-speed system clock oscillator, internal high-speed oscillator, or subsystem clock oscillator is operating
before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not
decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately
upon interrupt request generation and carrying out intermittent operations frequently.
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately
upon interrupt request generation.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation
3. The following sequence is recommended for operating current reduction of the A/D converter
4. It can be selected by the option byte whether the internal low-speed oscillator continues
STOP mode cannot be set while the CPU operates with the subsystem clock. The HALT
mode can be used when the CPU is operating on either the main system clock or the
subsystem clock.
operating with main system clock before executing STOP instruction.
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the STOP instruction.
oscillating or stops in the HALT or STOP mode. For details, see CHAPTER 22 OPTION BYTE.
CHAPTER 17 STANDBY FUNCTION
User’s Manual U17854EJ9V0UD