UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 191

• Manufacturer Part Number: UPD78F1146AGB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AGB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: F00F0H
(1) Peripheral enable register 0 (PER0)
Symbol
PER0
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. When setting the timer array unit, be sure to set TAU0EN = 1 first. If TAU0EN = 0, writing to
TAU0EN
RTCEN
2. Be sure to clear bit 1, 6 of the PER0 register to 0.
<7>
0
1
After reset: 00H
a control register of the timer array unit is ignored, and all read values are default values
(except for timer input select register 0 (TIS0), input switch control register (ISC), noise
filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4 (PM0, PM1, PM3, PM4), and
port registers 0, 1, 3, 4 (P0, P1, P3, P4)).
Stops supply of input clock.
• SFR used by the timer array unit cannot be written.
• The timer array unit is in the reset status.
Supplies input clock.
• SFR used by the timer array unit can be read/written.
Figure 6-4. Format of Peripheral Enable Register 0 (PER0)
6
0
R/W
CHAPTER 6 TIMER ARRAY UNIT
ADCEN
<5>
User’s Manual U17854EJ9V0UD
Control of timer array unit input clock
IIC0EN
<4>
SAU1EN
<3>
SAU0EN
<2>
1
0
TAU0EN
<0>
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