DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 127

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3.3
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.4
After reset release, MSTPCRA is initialized to H'3F, MSTPCRB and MSTPCRC are initialized to
H'FF, and all modules except the DTC enter module stop mode. Consequently, on-chip peripheral
module registers cannot be read or written to. Register reading and writing is enabled when the
module stop mode is exited.
4.4
Trace is enabled in interrupt control mode 2. Trace mode is not entered in interrupt control mode
0, irrespective of the state of the T bit. For details on the interrupt control mode, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is entered. In trace mode, a trace exception handling
occurs on completion of each instruction. After execution of trace exception handling, the T bit in
EXR is cleared to 0 and trace mode is canceled. Trace mode is not affected by interrupt masking.
Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts
are accepted even within the trace exception handling routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling
is not carried out after execution of the RTE instruction.
Interrupts after Reset
State of On-Chip Peripheral Modules after Reset Release
Trace Exception Handling
Rev. 6.00 Sep. 24, 2009 Page 79 of 928
Section 4 Exception Handling
REJ09B0099-0600