DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 515

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.9
13.9.1
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, see section 22, Power-Down Modes.
13.9.2
When framing error (FER) detection is performed, a break can be detected by reading the RxD pin
value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and
possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break,
even if the FER flag is cleared to 0, it will be set to 1 again.
13.9.3
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by DDR. This can be used to set the TxD pin to mark state (high level) or send a break
during serial data transmission. To maintain the communication line at mark state until TE is set to
1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port,
and 1 is output from the TxD pin. To send a break during serial transmission, first set PDR to 1
and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized
regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from
the TxD pin.
13.9.4
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
13.9.5
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DTC. Incorrect operation may
occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 13.33)
Usage Notes
Module Stop Mode Setting
Break Detection and Processing (Asynchronous Mode Only)
Mark State and Break Detection (Asynchronous Mode Only)
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Restrictions on Use of DTC
Section 13 Serial Communication Interface (SCI)
Rev. 6.00 Sep. 24, 2009 Page 467 of 928
REJ09B0099-0600