DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 528

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
Rev. 6.00 Sep. 24, 2009 Page 480 of 928
REJ09B0099-0600
Bit
7
6
5
4
3
2
1
0
Bit Name
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
2
C Bus Interface 2 (IIC2)
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I
0: This module is halted. (SCL and SDA pins are set to port
1: This bit is enabled for transfer operations. (SCL and
Reception Disable
This bit enables or disables the next receive operation
while TRS is 0 and until ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
In master mode with the I
lost, MST and TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of the TRS
bit should be made between transfer frames.
After data receive has been started in slave receive mode,
when the first seven bits of the receive data agree with the
slave address that is set to SAR and the eighth bit is 1,
TRS is automatically set to 1. If an overrun error occurs in
master mode with the clock synchronous serial format,
MST is cleared to 0 and slave receive mode is entered.
Operating modes are described below according to MST
and TRS combination. When clocked synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select 3 to 0
Set these bits according to the necessary transfer rate in
master mode (see table 14.2). During slave mode, these
bits are specified to ensure enough time for data setup in
transmit mode. When CKS3 is 0, the time is 10 tcyc, and
CKS3 is 1, 20 tcyc.
2
C Bus Interface Enable
function.)
SDA pins are bus drive state.)
2
C bus format, when arbitration is