DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 433

IC H8S/2505 MCU FLASH 176-LFBGA

DF2505BR26DV

Manufacturer Part Number
DF2505BR26DV
Description
IC H8S/2505 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2505BR26DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2505BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.3.3
RSTCSR controls to generate the internal reset signal when TCNT overflows, and selects the type
of internal reset signal. RSTCSR is initialized by a reset signal from the RES pin, and not by the
WDT internal reset signal caused by overflows.
Note:
Bit
7
6
5
4 to 0
*
Reset Control/Status Register (RSTCSR) (WDT_0 only)
Bit Name
WOVF
RSTE
RSTS
Only 0 can be written, to clear the flag.
Initial
Value
0
0
0
All 1
R/W
R/(W)* Watchdog Overflow Flag
R/W
R/W
Description
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written, to clear the flag.
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00)
in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is generated in
the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows.
Reset Select
Selects the type of internal reset, which is generated if
TCNT overflows during watchdog timer operation.
0: Power-on reset
1: Manual reset
Reserved
These bits are always read as 1 and cannot be
modified.
overflows. (Though this LSI is not reset, TCNT and
TCSR in WDT are reset.)
Rev. 6.00 Sep. 24, 2009 Page 385 of 928
Section 12 Watchdog Timer (WDT)
REJ09B0099-0600

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