DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 965

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
13.3.7 Serial Status
Register (SSR)
•
Smart Card Interface
Mode (When SMIF in
SCMR Is 1)
Page
413
414
Revision (See Manual for Details)
Table amended and note added
Bit
7
6
Bit
5
4
TDRE
RDRF
ORER
ERS
Bit Name
Bit Name
Initial
Value
1
0
Initial
Value
0
0
R/W
R/(W)*
R/(W)*
R/W
R/(W)*
R/(W)*
1
1
1
1
Rev. 6.00 Sep. 24, 2009 Page 917 of 928
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF
flag is still set to 1, an overrun error will occur and the
receive data will be lost.
Description
Overrun Error
Indicates that an overrun error occurred during reception,
causing abnormal termination.
[Setting condition]
•
The receive data prior to the overrun error is retained in
RDR, and the data received subsequently is lost. Also,
subsequent serial cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
•
The ORER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
Error Signal Status
Indicates that the status of an error, signal 1 returned
from the reception side at reception
[Setting condition]
•
[Clearing condition]
•
The ERS flag is not affected and retains its previous state
when the TE bit in SCR is cleared to 0.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data
can be written to TDR
When 0 is written to TDRE after reading TDRE = 1*
When the DTC*
request and writes data to TDR
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1*
When the DTC*
transfers data from RDR
When the next serial reception is completed while
RDRF = 1
When 0 is written to ORER after reading ORER = 1*
When the low level of the error signal is sampled
When 0 is written to ERS after reading ERS = 1*
2
2
is activated by a TXI interrupt
is activated by an RXI interrupt and
REJ09B0099-0600
3
3
3
3