DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 24

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4 Operation Descriptions ...................................................................................................... 589
17.5 Interrupt Sources................................................................................................................ 602
17.6 Usage Notes ....................................................................................................................... 603
Section 18 Controller Area Network (HCAN) [H8S/2556 Group].................... 609
18.1 Features.............................................................................................................................. 609
Rev. 6.00 Sep. 24, 2009 Page xxii of xlvi
REJ09B0099-0600
17.3.5 IEBus Master Unit Address Register 2 (IEAR2) .................................................. 564
17.3.6 IEBus Slave Address Setting Register 1 (IESA1)................................................. 564
17.3.7 IEBus Slave Address Setting Register 2 (IESA2)................................................. 565
17.3.8 IEBus Transmit Message Length Register (IETBFL) .......................................... 565
17.3.9 IEBus Transmit Buffer Register (IETBR) ............................................................ 566
17.3.10 IEBus Reception Master Address Register 1 (IEMA1) ........................................ 567
17.3.11 IEBus Reception Master Address Register 2 (IEMA2) ........................................ 568
17.3.12 IEBus Receive Control Field Register (IERCTL) ................................................ 568
17.3.13 IEBus Receive Message Length Register (IERBFL)............................................ 569
17.3.14 IEBus Receive Buffer Register (IERBR).............................................................. 570
17.3.15 IEBus Lock Address Register 1 (IELA1) ............................................................. 571
17.3.16 IEBus Lock Address Register 2 (IELA2) ............................................................. 571
17.3.17 IEBus General Flag Register (IEFLG) ................................................................. 572
17.3.18 IEBus Transmit/Runaway Status Register (IETSR) ............................................. 576
17.3.19 IEBus Transmit/Runaway Interrupt Enable Register (IEIET) .............................. 579
17.3.20 IEBus Transmit Error Flag Register (IETEF)....................................................... 580
17.3.21 IEBus Receive Status Register (IERSR)............................................................... 583
17.3.22 IEBus Receive Interrupt Enable Register (IEIER)................................................ 585
17.3.23 IEBus Receive Error Flag Register (IEREF) ........................................................ 586
17.4.1 Master Transmit Operation................................................................................... 589
17.4.2 Slave Receive Operation....................................................................................... 591
17.4.3 Master Reception .................................................................................................. 596
17.4.4 Slave Transmission............................................................................................... 599
17.6.1 Setting Module Stop Mode ................................................................................... 603
17.6.2 TxRDY Flag and Underrun Error ......................................................................... 603
17.6.3 RxRDY Flag and Overrun Error........................................................................... 604
17.6.4 Error Flag s in the IETEF ..................................................................................... 604
17.6.5 Error Flags in IEREF ............................................................................................ 605
17.6.6 Notes on Slave Transmission................................................................................ 606
17.6.7 Notes on DTC Specification ................................................................................. 607
17.6.8 Error Handling in Transmission............................................................................ 607
17.6.9 Power-Down Mode Operation.............................................................................. 608
17.6.10 Notes on Middle-Speed Mode .............................................................................. 608
17.6.11 Notes on Register Access ..................................................................................... 608