DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 128

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Exception Handling
Table 4.4
Legend:
1:
0:
⎯:
4.5
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. For details, see section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
4.6
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
Rev. 6.00 Sep. 24, 2009 Page 80 of 928
REJ09B0099-0600
Interrupt Control Mode
0
2
(EXR) are saved to the stack.
from the vector table to the PC, and program execution begins from that address.
(EXR) are saved to the stack.
from the vector table to the PC, and program execution starts from that address.
Set to 1
Cleared to 0
Retains value prior to execution
Interrupt Exception Handling
Trap Instruction Exception Handling
State of CCR and EXR after Trace Exception Handling
I
Trace exception handling cannot be used.
1
CCR
UI
⎯
I2 to I0
⎯
EXR
0
T