DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 417

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.6
If the CKS2 to CKS0 bits in one of TCR_0 and TCR_1 (or TCR_2 and TCR_3) are set to B'100,
the 8-bit timers (TMR) of the two channels are cascaded. With this configuration, a single 16-bit
timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 (channel 2) can be
counted by the timer of channel 1 (channel 3) (compare-match count mode). In the case that
channel 0 is connected to channel 1 in cascade, the timer operates as described below.
11.6.1
When the CKS2 to CKS0 bits in TCR_0 are set to B'100, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
• Setting of compare-match flags
• Counter clear specification
• Pin output
11.6.2
When the CKS2 to CKS0 bits in TCR_1 are B'100, TCNT_1 counts compare-match A for channel
0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the
settings for each channel.
⎯ The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
⎯ The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
⎯ If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,
⎯ The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot
⎯ Control of output from the TMO0 pin by the OS3 to OS0 bits in TCSR_0 is in accordance
⎯ Control of output from the TMO1 pin by the OS3 to OS0 bits in TCSR_1 is in accordance
the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-
match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is cleared even if
counter clear by the TMRI01 pin has also been set.
be cleared independently.
with the 16-bit compare-match conditions.
with the lower 8-bit compare-match conditions.
Operation with Cascaded Connection
16-Bit Count Mode
Compare-Match Count Mode
Rev. 6.00 Sep. 24, 2009 Page 369 of 928
Section 11 8-Bit Timers (TMR)
REJ09B0099-0600