DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 550

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
input when MST is 0. For transmit mode operation timing, see figure 14.14. The transmission
procedure and operations in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
Receive Operation: In receive mode, data is latched at the rise of the transfer clock. The transfer
clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation
timing, see figure 14.15. The reception procedure and operations in receive mode are described
below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
Rev. 6.00 Sep. 24, 2009 Page 502 of 928
REJ09B0099-0600
processing
(Output)
ICDRS
ICDRT
TDRE
SDA
SCL
TRS
User
setting)
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
setting)
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
[2] Set TRS
2
C Bus Interface 2 (IIC2)
[3] Write data
to ICDRT
Data 1
Bit 0
Figure 14.14 Transmit Mode Operation Timing
1
[3] Write data
to ICDRT
Bit 1
2
Data 1
Bit 6
7
Data 2
Bit 7
8
Bit 0
Data 2
1
Bit 6
7
[3] Write data
Bit 7
to ICDRT
8
Data 3
[3] Write data
Data 3
Bit 0
to ICDRT
1