DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 545

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(Master output)
14.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
see figures 14.9 and 14.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
(Master output)
(Slave output)
processing
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
with TDRE = 1. When TEND is set, clear TEND.
ICDRR
SCL
ICDRS
SDA
SDA
RDRF
RCVD
User
Slave Transmit Operation
Data n-1
A
Figure 14.8 Master Receive Mode Operation Timing (2)
9
[5] Read ICDRR after setting RCVD
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
[7] Read ICDRR,
6
and clear RCVD
Rev. 6.00 Sep. 24, 2009 Page 497 of 928
Bit 1
7
Section 14 I
Bit 0
Data n
8
A/A
9
Data n
[6] Issue stop
2
C Bus Interface 2 (IIC2)
condition
REJ09B0099-0600
[8] Set slave
receive mode