DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 208

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller
7.8
When this LSI accesses external address space, it can insert one-state idle cycle (T
cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read
cycle.
Figure 7.27 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Rev. 6.00 Sep. 24, 2009 Page 160 of 928
REJ09B0099-0600
CS (area A)
CS (area B)
Address bus
Idle Cycle
Data bus
RD
φ
(a) Idle cycle not inserted
(ICIS1 = 0)
T
1
Bus cycle A
Figure 7.27 Example of Idle Cycle Operation (1)
Long output floating time
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
φ
T
1
Bus cycle A
(b) Idle cycle inserted
(Initial value: ICIS1 = 1)
T
2
T
3
T
Bus cycle B
I
T
I
1
) between bus
T
2