DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 516

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI
•
13.9.6
• Transmission
Rev. 6.00 Sep. 24, 2009 Page 468 of 928
REJ09B0099-0600
reception data full interrupt (RXI).
Operation should be stopped (by clearing TE, TIE, and TEIE bits to 0) before making a
module stop mode, software standby mode, or watch mode transition. TSR, TDR, and SSR are
reset. The output pin states in module stop mode, software standby mode, or watch mode
depend on the port settings, and become high-level output after the relevant mode is cleared. If
a transition is made during transmission, the data being transmitted will be undefined. When
transmitting without changing the transmit mode after the relevant mode is cleared,
transmission can be started by setting TE to 1 again, and performing the following sequence:
SSR read -> TDR write -> TDRE clearance. To transmit with a different transmit mode after
clearing the relevant mode, the procedure must be started again from initialization. Figure
13.34 shows a sample flowchart for mode transition during transmission. Port pin states are
shown in figures 13.35 and 13.36.
Operation should also be stopped (by clearing TE, TIE, and TEIE bits to 0) before making a
transition from transmission by DTC transfer to module stop mode, software standby mode, or
watch mode. To perform transmission with the DTC after the relevant mode is cleared, setting
the TE and TIE bits to 1 will set the TXI flag and start DTC transmission.
The flags are automatically cleared to 0 by the DTC during the data transfer only when the
DISEL bit in DTC is 0 with the transfer counter other than 0. When the DISEL bit in the
corresponding DTC is 1, or both the DISEL bit and the transfer counter are 0, give the CPU
an instruction to clear flags. Note that, particularly during transmission, the TDRE flag that is
not cleared by the CPU causes incorrect transmission.
Operation in Case of Mode Transition
SCK
TDRE
Serial data
Note: When operating on an external clock, set t >4 clocks.
Figure 13.33 Example of Clocked Synchronous Transmission by DTC
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7