DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 640

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
(c) Setting the IEBus Receive Interrupt Enable Register (IEIER)
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2)
1. Set the start address of the RAM which stores the register information necessary for the DTC
2. Specify the following from the start address of the RAM.
3. Set DTCEG6 in the DTC enabler register G (DTCERG) to enable the RxRDY interrupt
Because the above settings are performed before the frame reception, the length of data to be
received cannot be decided. Accordingly, the maximum number of transfer bytes in one frame is
specified as the DTC transfer count.
If the DTC is specified after reception starts, the above settings are performed in the receive start
(RxS) interrupt handling routine. In this case, the transfer count must be the same value as the
contents of the IEBus receive message length register (IERBFL).
(3)
Figure 17.9 shows the slave reception flow. Numbers in the following description correspond to
the number in Figure 17.9. In this example, the DTC is specified when the frame reception starts.
1. After the broadcast reception has been completed, the slave reception is performed. The
Rev. 6.00 Sep. 24, 2009 Page 592 of 928
REJ09B0099-0600
Specify the master unit address and specify the communications mode in IEAR1. Compare
with the slave address in the communications frame and receive the frame if matched.
Enable RxRDY (IERxI), RxS, and RxE (IERSI) interrupts.
transfer in the vector address (H'000004D2) to be accessed when a DTC transfer request is
generated.
⎯ Transfer source address (SAR): Address (H'FFF80D) of the IEBus receive buffer register
⎯ Transfer destination address (DAR): Start address of the RAM which stores data received
⎯ Transfer count (CRA): Maximum number of transfer bytes in one frame in the transfer
(IETxI).
receive broadcast bit status flag (RSS) in IEFLG retains the previous frame information (set to
1) until the receive start detection flag (RxS) is set to 1. If the RSS flag changes at the timing
of header reception, the interrupt handling of the broadcast reception completion must be
DTC Initialization
Slave Reception Flow
(IERBR).
from the data field.
mode.