DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 754

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory
128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is updated
in 128-byte units and programming is repeated.
When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the dummy data to be added is H'FF, the program processing period can be
shortened.
(a) Select the on-chip program to be downloaded and specify a download destination
(b) Program H'A5 in FKEY
(c) 1 is written to the SCO bit of FCCS and then download is executed.
Rev. 6.00 Sep. 24, 2009 Page 706 of 928
REJ09B0099-0600
When the PPVS bit of FPCS is set to 1, the programming program is selected. Several
programming/erasing programs cannot be selected at one time. If several programs are set,
download is not performed and a download error is returned to the SS bit in DPFR. The start
address of a download destination is specified by FTDAR.
If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for download
request.
To write 1 to the SCO bit, the following conditions must be satisfied.
⎯ RAM emulation mode is canceled.
⎯ H'A5 is written to FKEY.
⎯ The SCO bit writing is executed in the on-chip RAM.
When the SCO bit is set to 1, download is started automatically. When the program execution
processing returned to the user procedure program, the SCO is cleared to 0. Therefore, the
SCO bit cannot be confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of DPFR. Before the SCO bit
is set to 1, incorrect determination must be prevented by setting the one byte of the start
address (to be used as DPFR) specified by FTDAR to a value other than the return value
(H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcomputer processing. Four NOP
instructions are executed immediately after the instructions that set the SCO bit to 1.
⎯ The user-MAT space is switched to the on-chip program storage area.
⎯ After the selection condition of the download program and the FTDAR setting are checked,
⎯ FPCS, FECS, and the SCO bit in FCCS are cleared to 0.
⎯ The return value is set to the DPFR parameter.
the transfer processing to the on-chip RAM specified by FTDAR is executed.