DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 210

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 7.29.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Table 7.4 shows the pin states in an idle cycle.
Table 7.4
Rev. 6.00 Sep. 24, 2009 Page 162 of 928
REJ09B0099-0600
Pins
A23 to A0
D15 to D0
CSn
AS
RD
HWR
LWR
Address bus
CS (area A)
CS (area B)
Pin States in Idle Cycle
Figure 7.29 Relationship between Chip Select (CS) and Read (RD)
RD
φ
Possibility of overlap between
CS (area B) and RD
T
(a) Idle cycle not inserted
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
Address bus
CS (area A)
CS (area B)
Pin State
Contents of next bus cycle
High impedance
High
High
High
High
High
RD
φ
T
1
Bus cycle A
(b) Idle cycle inserted
(Initial value: ICIS1 = 1)
T
2
T
3
T
Bus cycle B
I
T
1
T
2