DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 595

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The message length has eight bits and is output MSB first. Table 17.3 shows the number of
transfer bytes.
Table 17.3 Contents of Message Length bits
Note:
This field operation differs depending on the value of bit 3 in the control field: master
transmission (bit 3 in the control bits is 1) or master reception (bit 3 in the control bits is 0).
(a) Master Transmission
(b) Master Reception
Message Length bits (Hexadecimal)
H'01
H'02
.
.
H'FF
H'00
The master unit outputs the message length bits and parity bit. When the parity is correct, the
slave unit returns the acknowledgement and enters the following data field. Note that the slave
unit does not return the acknowledgement in broadcast communications.
In addition, when the parity is not correct, the slave unit decides that the message length field
is not correctly received, does not return the acknowledgement, and returns to the waiting
(monitor) state. In this case, the master unit also returns to the waiting state, and
communications end.
The slave unit outputs the message length bits and parity bit. When the parity is correct, the
master unit returns the acknowledgement.
When the parity is not correct, the master unit decides that the message length bits are not
correctly received, does not return the acknowledgement, and returns to the waiting state. In
this case, the slave unit also returns to the waiting state, and communications end.
*
If a number greater than the maximum number of transfer bytes in one frame is
specified, communications are performed in multiple frames depending on the
communications mode. In this case, the message length bits indicate the number of
remaining communications data after the first transfer. In this LSI, after the first transfer,
the message length bits must be specified to the number of remaining communications
data by a program, since these bits are not automatically specified by the hardware.
Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Number of Transfer Bytes
1 byte
2 bytes
.
.
255 bytes
256 bytes
Rev. 6.00 Sep. 24, 2009 Page 547 of 928
REJ09B0099-0600