DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 506

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
13.7.6
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 13.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving end after transmission of one frame is
2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Figure 13.28 shows a flowchart for transmission. A sequence of transmit operations can be
performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a
transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and
a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is
designated beforehand as a DTC activation source, the DTC will be activated by the TXI request,
and transfer of the transmit data will be carried out. At this moment, when the DISEL bit in DTC
is 0 and the transfer counter is other than 0, the TDRE and TEND flags are automatically cleared
to 0 when data is transferred by the DTC. When the DISEL bit in the corresponding DTC is 1, or
both the DISEL bit and the transfer counter are 0, flags are not cleared although the transfer data is
written to TDR by DTC. Consequently, give the CPU an instruction of flag clear processing. In
addition, in the event of an error, the SCI retransmits the same data automatically. During this
period, the TEND flag remains cleared to 0 and the DTC is not activated. Therefore, the SCI and
DTC will automatically transmit the specified number of bytes in the event of an error, including
retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so
the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of
an error, and the ERS flag will be cleared.
When performing transfer using the DTC, it is essential to set and enable the DTC before carrying
out SCI setting. For details on the DTC setting procedures, see section 8, Data Transfer Controller
(DTC).
Rev. 6.00 Sep. 24, 2009 Page 458 of 928
REJ09B0099-0600
complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 by the time the next
parity bit is sampled.
is received. Data is retransferred from TDR to TSR, and retransmitted automatically.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated. Writing transmit data to TDR transfers the next transmit data.
Serial Data Transmission (Except for Block Transfer Mode)