DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 543

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, see figures
14.7 and 14.8. The reception procedure and operations in master receive mode are shown below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If, while
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
RDRF is set to 1, the reading of ICDRR is delayed by other processing and does not occur by
the falling edge of the 8th clock pulse, set RCVD to 1 and perform one-byte data transfer.
This enables the issuance of the stop condition after the next reception.
Master Receive Operation
Rev. 6.00 Sep. 24, 2009 Page 495 of 928
Section 14 I
2
C Bus Interface 2 (IIC2)
REJ09B0099-0600