DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 560

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
14.7.4
In master receive mode, when SCL is fixed low on the falling edge of the 8th clock while the
RDRF bit is set to 1 and ICDRR is read around the falling edge of the 8th clock, the clock is only
fixed low in the 8th clock of the next round of data reception. The SCL is then released from its
fixed state without reading ICDRR and the 9th clock is output. As a result, some receive data is
lost.
Ways to avoid this phenomenon are listed below.
• Read ICDRR in master receive mode before the rising edge of the 8th clock.
• Set RCVD to 1 in master receive mode and perform communication in units of one byte.
14.7.5
In multi-master usage when the IIC transfer rate setting of this LSI is lower than those of the other
masters, unexpected length of SCL may occasionally be output. To avoid this, the specified value
must be greater than or equal to the value produced by multiplying the fastest transfer rate among
the other masters by 1/1.8. For example, when the transfer rate of the fastest bus master among the
other bus masters is 400 kbps, the transfer rate of the IIC of this LSI must be set to at least 223
kbps (= 400/1.8).
14.7.6
When master transmission is selected by consecutively manipulating the MST and TRS bits in
multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for
TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode (MST =
1, TRS = 1).
Ways to avoid this effect are listed below.
• Use the MOV instruction to set MST and TRS in multi-master usage.
• When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and
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REJ09B0099-0600
TRS = 0 is not confirmed, set MST = 0 and TRS = 0 again.
Usage Note on Master Receive Mode
Restriction on Setting of Transfer Rate in Use of Multi-Master
Restriction on Use of Bit Manipulation Instructions to Set MST and TRS when
Multi-Master Is Used
2
C Bus Interface 2 (IIC2)