DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 13

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.4
5.5
5.6
Section 6 PC Break Controller (PBC) .................................................................115
6.1
6.2
6.3
6.4
5.3.2
5.3.3
5.3.4
Interrupt Sources.................................................................................................................. 94
5.4.1
5.4.2
5.4.3
Operation ........................................................................................................................... 100
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Usage Notes ....................................................................................................................... 112
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
Features.............................................................................................................................. 115
Register Descriptions ......................................................................................................... 116
6.2.1
6.2.2
6.2.3
6.2.4
Operation ........................................................................................................................... 118
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Usage Notes ....................................................................................................................... 121
6.4.1
6.4.2
6.4.3
6.4.4
IRQ Enable Register (IER) ..................................................................................... 90
IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 91
IRQ Status Register (ISR)....................................................................................... 93
External Interrupts .................................................................................................. 94
Internal Interrupts ................................................................................................... 95
Interrupt Exception Handling Vector Table............................................................ 95
Interrupt Control Modes and Interrupt Operation ................................................. 100
Interrupt Control Mode 0 ...................................................................................... 103
Interrupt Control Mode 2 ...................................................................................... 105
Interrupt Exception Handling Sequence ............................................................... 107
Interrupt Response Times ..................................................................................... 109
DTC Activation by Interrupt................................................................................. 110
Contention between Interrupt Generation and Disabling...................................... 112
Instructions That Disable Interrupts...................................................................... 113
When Interrupts Are Disabled .............................................................................. 113
Interrupts during Execution of EEPMOV Instruction........................................... 114
IRQ Interrupt ........................................................................................................ 114
NMI Interrupt Usage Notes .................................................................................. 114
Break Address Register A (BARA) ...................................................................... 116
Break Address Register B (BARB) ...................................................................... 117
Break Control Register A (BCRA) ....................................................................... 117
Break Control Register B (BCRB)........................................................................ 118
PC Break Interrupt Due to Instruction Fetch ........................................................ 118
PC Break Interrupt Due to Data Access................................................................ 119
Notes on PC Break Interrupt Handling ................................................................. 119
Operation in Transitions to Power-Down Modes ................................................. 119
When Instruction Execution Is Delayed by One State.......................................... 120
Module Stop Mode Setting ................................................................................... 121
PC Break Interrupts .............................................................................................. 121
CMFA and CMFB ................................................................................................ 121
PC Break Interrupt when DTC Is Bus Master ...................................................... 121
Rev. 6.00 Sep. 24, 2009 Page xi of xlvi
REJ09B0099-0600