DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 753

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
The procedures for download, initialization, and programming are shown in figure 20.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for
Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing is
executed before writing.
Programming Procedure in User Program Mode
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
Set the FPEFEQ and
FUBRA parameters
Set SCO to 1 and
procedure program
execute download
Start programming
specify download
Set FKEY to H'A5
Clear FKEY to 0
DPFR = 0?
Initialization
FPFR = 0?
1
Yes
Yes
Initialization error processing
Download error processing
No
No
Figure 20.11 Programming Procedure
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
No
Disable interrupts and bus
Rev. 6.00 Sep. 24, 2009 Page 705 of 928
JSR FTDAR setting + 16
Set parameters to ER1
(FMPAR and FMPDR)
procedure program
End programming
Set FKEY to H'5A
master operation
Clear FKEY to 0
programming is
other than CPU
Required data
Programming
FPFR = 0?
completed?
and ER0
1
Yes
Yes
Section 20 Flash Memory
Clear FKEY and
error processing
No
programming
REJ09B0099-0600
(i)
(j)
(k)
(l)
(m)
(n)
(o)