DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 482

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Rev. 6.00 Sep. 24, 2009 Page 434 of 928
REJ09B0099-0600
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Read ORER, PER, and
PER FER ORER = 1
All data received?
FER flags in SSR
Start reception
Initialization
RDRF = 1
Figure 13.9 Sample Serial Reception Data Flowchart (1)
<End>
Yes
Yes
No
(Continued on next page)
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] [3] Receive error processing and break
[4] SCI status check and receive data read:
[5] Serial reception continuation procedure:
Note: * The case, where the RDRF flag is
The RxD pin is automatically
designated as the receive data input
pin.
detection:
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
The RDRF flag is cleared automatically
when DTC* is activated by an RXI
interrupt and the RDR value is read.
automatically cleared by DTC,
occurs only when the DISEL bit in DTC is 0
with the transfer counter other than 0.
Therefore, when the DISEL bit is 1, or
both the DISEL bit and the transfer counter are 0,
give the CPU an instruction to clear the RDRF flag.