DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 19

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 8-Bit Timers (TMR)...........................................................................353
11.1 Features.............................................................................................................................. 353
11.2 Input/Output Pins ............................................................................................................... 355
11.3 Register Descriptions ......................................................................................................... 355
11.4 Operation ........................................................................................................................... 364
11.5 Operation Timing............................................................................................................... 365
11.6 Operation with Cascaded Connection................................................................................ 369
11.7 Interrupt Sources................................................................................................................ 370
11.8 Usage Notes ....................................................................................................................... 371
10.9.6 Contention between TGR Write and Compare Match .......................................... 346
10.9.7 Contention between Buffer Register Write and Compare Match ......................... 347
10.9.8 Contention between TGR Read and Input Capture............................................... 348
10.9.9 Contention between TGR Write and Input Capture.............................................. 349
10.9.10 Contention between Buffer Register Write and Input Capture ............................. 350
10.9.11 Contention between Overflow/Underflow and Counter Clearing......................... 351
10.9.12 Contention between TCNT Write and Overflow/Underflow................................ 352
10.9.13 Multiplexing of I/O Pins ....................................................................................... 352
10.9.14 Interrupts in Module Stop Mode........................................................................... 352
11.3.1 Timer Counter (TCNT)......................................................................................... 356
11.3.2 Time Constant Register A (TCORA).................................................................... 356
11.3.3 Time Constant Register B (TCORB) .................................................................... 357
11.3.4 Timer Control Register (TCR).............................................................................. 357
11.3.5 Timer Control/Status Register (TCSR)................................................................. 359
11.4.1 Pulse Output.......................................................................................................... 364
11.5.1 TCNT Incrementation Timing .............................................................................. 365
11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs............... 366
11.5.3 Timing of Timer Output When a Compare-Match Occurs ................................... 366
11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs ..................... 367
11.5.5 TCNT External Reset Timing............................................................................... 367
11.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 368
11.6.1 16-Bit Count Mode ............................................................................................... 369
11.6.2 Compare-Match Count Mode ............................................................................... 369
11.7.1 Interrupt Sources and DTC Activation ................................................................. 370
11.7.2 A/D Converter Activation..................................................................................... 370
11.8.1 Setting Module Stop Mode ................................................................................... 371
11.8.2 Contention between TCNT Write and Clear......................................................... 371
11.8.3 Contention between TCNT Write and Increment ................................................. 372
11.8.4 Contention between TCOR Write and Compare-Match ....................................... 373
11.8.5 Contention between Compare-Matches A and B.................................................. 373
Rev. 6.00 Sep. 24, 2009 Page xvii of xlvi
REJ09B0099-0600