DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 184

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-
bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is
always set.
Number of access states: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space.
With the burst ROM interface, the number of access states may be determined without regarding
to ASTCR.
When 2-state access space is designated, wait insertion is disabled.
Number of program wait states: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WCRH and WCRL.
From 0 to 3 program wait states can be selected.
Table 7.2
7.4.3
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and sections 7.6, Basic Bus Interface, and 7.7, Burst ROM Interface, on each memory
interface should be referred to for further details.
Rev. 6.00 Sep. 24, 2009 Page 136 of 928
REJ09B0099-0600
ABWCR
ABWn
0
1
Bus Interface for Each Area
ASTCR
ASTn
0
1
0
1
Bus Specifications for Each Area (Basic Bus Interface)
Wn1
⎯
0
1
⎯
0
1
WCRH, WCRL
Wn0
⎯
0
1
0
1
⎯
0
1
0
1
Bus Width
16
8
Bus Specifications (Basic Bus Interface)
Number of Access
States
2
3
2
3
Number of Program
Wait States
0
0
1
2
3
0
0
1
2
3