mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 13
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mt9072av2
Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT9072AV2.pdf
(275 pages)
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MT9072AV2
Manufacturer:
ZARLINK
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15.0 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
16.0 JTAG (Joint Test Action Group) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
17.0 MT9072 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
14.2 E1 Maintenance and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15.1 Interrupt Status Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
15.2 Interrupt Servicing Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
15.3 T1 Interrupt Vector and Interrupt Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
15.4 E1 Interrupt Vector and Interrupt Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
15.5 E1 Interrupt Source and Interrupt Status Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
16.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
16.2 Test Access Port (TAP) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
16.3 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
16.4 JTAG Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
17.1 T1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
17.2 E1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.1.7 T1 Per Timeslot Trunk Conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.2.1 E1 Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.2.2 E1 Per Timeslot Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.2.3 E1 Per Timeslot Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.2.4 E1 Pseudo-Random Bit Sequence (PRBS) Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.2.5 E1 A-law Milliwatt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.2.6 E1 Alarms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.2.7 E1 Automatic Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
15.1.1 Interrupt Related Control Bits and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
15.2.1 Polling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
15.2.2 Vector Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
16.4.1 Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
17.1.1 Register Address (000 - FFF) Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
17.1.2 Interrupt Mask Registers Address (Y40-Y4F) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
17.1.3 Master Control Registers (Y00 to YF0 ) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
17.1.4 Master Status Registers(Y10-Y18)Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
17.1.5 Latched Status Registers (Y20 - Y2F) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
17.1.6 Interrupt Status Registers (Y30 - Y3F) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
17.1.7 Interrupt Mask Registers (Y40 - Y4F) Bit Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
17.1.8 Per Channel Control and Data (Y50 - YAF) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.1.9 Master Control Registers (YF1 to YF7) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
17.1.10 Global Control and Status Registers (900 - 91F) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . 149
17.2.1 Register Address (000 - FFF) Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
17.2.2 Register Address (Y00 - YFF) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
17.1.1.1 Framer Address (0XX-9XX) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
17.1.1.2 Register Group Address (Y00 - YFF) Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
17.1.1.3 Global Control and Status Register (900-91F) Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 109
17.1.1.4 Master Control Registers Address (Y00-Y0F, YF0 to YFF) Summary . . . . . . . . . . . . . . . . 110
17.1.1.5 Master Status Registers Address (Y10-Y1F) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
17.1.1.6 Latched Status Registers Address (Y20-Y2F) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 113
17.1.1.7 Interrupt Status Registers Address (Y30-Y3F) Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 114
17.2.1.1 Framer Address (000-FFF) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
17.2.1.2 Register Group Address (Y00 - YFF) Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
17.2.1.3 Global Control and Status Register (900-91F) Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 160
17.2.2.1 Master Control Registers Address (Y00-Y0F, YF0-YFF) Summary . . . . . . . . . . . . . . . . . . 161
17.2.2.2 Master Status Registers Address (Y10-Y1F) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
17.2.2.3 Latched Status Registers Address (Y20-Y2F) Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table of Contents
Zarlink Semiconductor Inc.
MT9072
13
Data Sheet
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