mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 86
mt9072av2
Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT9072AV2.pdf
(275 pages)
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c) Local and Remote Timeslot Loopback. Remote timeslot loopback control bit RTSL = 0 normal; RTSL = 1
activate, will loop around transmit ST-BUS timeslots to the DSTo stream. Local timeslot loopback bits LTSL = 0
normal; LTSL = 1 activate, will loop around receive PCM30 timeslots towards the remote PCM30 end.
d) Framer Remote loopback - Internally connects RPOS and RNEG of one framer to TPOS and TNEG respectively
of one of the other integrated framers.
Bit RLBK01, RLBK23, RLBK45, RLBK67 = 0 normal; = 1 activate.
8 Mbit/s mode:
Bit RLBK8 = 0 normal; = 1 activate.
e) Framer ST-BUS loopback - Internally connects DSTi of one framer to DSTo of one of the other integrated
framers.
Bit SLBK01, SLBK23, SLBK45, SLBK67 = 0 normal; = 1 activate.
8 Mbit/s mode:
Bit SLBK8 = 0 normal; = 1 activate.
System
System
System
PCM30
PCM30
DSTo[0]
DSTi[0]
DSTi
DSTo
Rx
Tx
Rx
Tx
DSTo
DSTi
MT9072 Framer 0,2,4,6
MT9072 Framer 0-3
MT9072 Framer 0,2,4,6
MT9072 Framer 0-3
MT9072
Tx
Rx
Tx
Rx
DSTo
DSTi
DSTi[0]
DSTo[0]
Tx
Rx
System
System
PCM30
PCM30
PCM30
Zarlink Semiconductor Inc.
DSTi[4]
DSTo[4]
DSTi
MT9072
DSTo
Rx
Rx
Tx
Tx
86
MT9072 Framer 1,3,5,7
MT9072 Framer 1,3,5,7
MT9072 Framer 4-7
MT9072 Framer 4-7
DSTo
DSTi
Tx
Tx
Rx
Rx
DSTi[4]
DSTo[4]
PCM30
PCM30
System
System
Data Sheet
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