mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 132

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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17.1.5
Tables 96 and 103 describe the bit functions of each of the Latched Status Registers in the MT9072 for T1. Each
register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2 with
Y=2 ... and Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB) A
latched status registers will be reset in the inactive state upon reset.
15-0
Bit
7-0
Bit
RCRC15-0 Received CRC. This register contains the CRC received from the transmitter. These bits
RXFIFO7-0 Receive FIFO.This is the received data byte read from the RX FIFO. The status bits of
Latched Status Registers (Y20 - Y2F) Bit Functions
Name
Name
are as the transmitter sent them, the LSB of the FCS sequence is MSB in this register. This
register is updated at the end of each received packet and therefore should be read when
end of packet is detected.
this byte can be read from the status register. The FIFO status is not changed
immediately when a write or read occurs. It is updated after the data has settled and the
transfer to the last available position has finished.
Note that if the HDLC receiver is connected to an receive T1 channel, the bit that arrived
first is stored in the least significant bit of the receive FIFO.
Table 93 - HDLC Receive CRC(Y1E) (T1)
Table 94 - Receive FIFO(Y1F) (T1)
Zarlink Semiconductor Inc.
MT9072
132
Functional Description
Functional Description
11
,A
Data Sheet
10
A
9
A
8
). All

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