mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 89

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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14.0
14.1
14.1.1
Six types of error conditions can be inserted into the transmit DS1 data stream through control bits, which are
located in address Y03 -Transmit Error Control Word. These error events include bipolar violation errors (BPVE),
CRC-6 errors (CRCE), Ft errors (FTE), Fs errors (FSE), payload errors (PERR) and a loss of signal condition
(LOSE). If LOSE is one the selected framer transmits an all zeros signal (no pulses) and zero code suppression is
overridden. If LOSE bit is zero, data is transmitted normally.
14.1.2
There are 24 per timeslot control registers occupying a total of 24 unique addresses (Y90-YA7). Each register
controls a transmit timeslot and the equivalent channel data on DSTo. For example, register address Y90 of the first
per timeslot control register contains program control for transmit timeslot 0 and DSTo channel 0.
14.1.3
Any channel or combination of channels may be looped from transmit (sourced from DSTi) to receive (output on
DSTo) ST-BUS channels. When bit 4 (LTSL) in the Per Timeslot Control Word(Y90-YA7) is set the data from the
equivalent transmit channel is looped back onto the equivalent receive timeslot.
Any channel or combination of channels may be looped from receive (sourced from the line data) to transmit
(output onto the line) channels. When bit 5 (RTSL) in the Per Timeslot Control Word is set the data from the
equivalent receive timeslot is looped back onto the equivalent transmit timeslot.
PRBS Error Counter
PRBS CRC-4 MF
Counter
Loss of Sync
Counter
E-bit Error Counter
BPV Error Counter
CRC-4 Error
Counter
FAS Bit Error
Counter
FAS Error Counter
Description
T1 Maintenance and Alarms
Maintenance and Alarms
T1 Error Insertion
T1 Per Timeslot Control
T1 Per Timeslot Looping
Counter
CEC15-0
EEC15-0
VEC15-0
PEC7-0
PCC7-0
BEC7-0
SLC7-0
FEC7-0
Bits
Table 43 - Error Counter and Event Dependency (E1)
Address
Y1A
Y1A
Y15
Y15
Y16
Y17
Y18
Y19
Source Interrupt Status Bits
BSYNC
CRCS1
CRCS2
CALN
REB1
REB2
Zarlink Semiconductor Inc.
Bit
MT9072
Indication Overflow Description
BSYNC
89
PEI
EEI
VEI
CEI
BEI
FEI
NA
PCO
PEO
EEO
VEO
CEO
BEO
FEO
SLO
NA
NA
NA
E-bit Error
Count Latch
BPV Error
Count Latch
CRC-4 Error
Count Latch
FAS Bit Error
Count Latch
FAS Error
Count Latch
1 Second Latch
CEL15-0
EEL15-0
VEL15-0
BEL7-0
FEL7-0
Bit
NA
NA
NA
Data Sheet
Address
Y2A
Y2B
Y2B
Y28
Y29
NA
NA
NA

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