mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 43

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

4.0
4.1
PCM30 (E1) basic frames are 256 bits long and are transmitted at a frame repetition rate of 8000 Hz, which results
in an aggregate bit rate of 256 bits x 8000/sec = 2.048 Mbits/sec. The actual bit rate is 2.048 Mbit/s +/-50 ppm
encoded in HDB3 (High Density Bipolar 3) format. Basic frames are divided into 32 timeslots numbered 0 to 31, see
Figure 6. Each timeslot is 8 bits in length and is transmitted most significant bit first (numbered bit 1). This results in
a single timeslot data rate of 8 bits x 8000/sec. = 64 kbit/s.
It should be noted that the Zarlink ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit of an
eight bit channel is numbered bit 7, see Figure 5. Therefore, ST-BUS bit 7 is synonymous with PCM30 bit 1; bit 6
with bit 2: and so on, see Zarlink Application Note MSAN-126 for more details on the ST-BUS.
Tables 4 and 5 show the mapping between the ST-BUS channels and the PCM30 timeslots.
When the device is in IMA (Inverse Mux for ATM) mode the mapping between the ST-BUS Channels and the
PCM30 timeslots is according to Table 4.
PCM30 timeslot 0 is reserved for basic frame alignment, CRC-4 multiframe alignment and the communication of
maintenance information (facility data link). In most configurations timeslot 16 is reserved for either Channel
Associated Signaling (CAS or ABCD bit signaling) or Common Channel Signaling (CCS). For V5.2 applications,
timeslots 15, 16 and 31 may be used for CCS. The remaining timeslots are called channels and carry either PCM
encoded voice signals or digital data. Channel alignment and bit numbering is consistent with timeslot alignment
and bit numbering. However, channels are numbered 1 to 30 and relate to timeslots as per Table 6.
PCM30 Timeslots
ST-BUS Channels
(DSTi/o and CSTi/o)
PCM30 Timeslots
ST-BUS Channels
(DSTi/o and CSTi/o)
PCM30 Timeslots
ST-BUS
Chan(DSTi/o F1/5
and CSTi/o) F2/6
PCM30 Timeslots
ST-BUS
Chan(DSTi/o F1/5
and CSTi/o) F2/6
Table 5 - ST-BUS Channel vs. PCM30 Timeslot Relationship for 8.192 Mbit/s DST/CST Streams (E1)
E1 Interface to the System Backplane
PCM30 Interface (E1)
Table 4 - ST-BUS Channel vs. PCM30 Timeslot for 2.048 Mbit/s DST/CST Streams (E1)
F0/4
F3/7
F0/4
F3/7
16
64
65
66
67
0
0
1
2
3
17
68
69
70
71
1
4
5
6
7
16
16
0
0
10
18
72
73
74
75
11
2
8
9
17
17
1
1
12
13
14
15
19
76
77
78
79
3
18
18
2
2
16
17
18
19
20
80
81
82
83
4
19
19
Zarlink Semiconductor Inc.
3
3
20
21
22
23
21
84
85
86
87
5
20
20
MT9072
4
4
24
25
26
27
22
88
89
90
91
6
43
21
21
5
5
28
29
30
31
23
92
93
94
95
7
22
22
6
6
32
33
34
35
24
96
97
98
99
8
23
23
7
7
100
101
102
103
36
37
38
39
25
9
24
24
8
8
104
105
106
107
10
40
41
42
43
26
25
25
9
9
10
10
26
26
108
109
110
111
11
44
45
46
47
27
27
27
11
11
112
113
114
115
12
48
49
50
51
28
12
12
28
28
116
117
118
119
13
52
53
54
55
29
13
13
29
29
Data Sheet
120
121
122
123
14
56
57
58
59
30
30
30
14
14
124
125
126
127
15
15
31
31
15
60
61
62
63
31