mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 212

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

17.2.11
Table 192 describes the bit functions of each (5 registers in total, one register for each bit position) of the Transmit
National Bits Data Registers in the MT9072. Each register is repeated for each of the 8 framers. Framer 0 is
addressed with Y=0, Framer 1 with Y=1, Framer 2 with Y=2 and so on up to Framer 7 with Y=7 (where Y represents
the 4 most significant address bits (MSB) A11-A8). In addition, a simultaneous write to all 8 framers is possible by
setting the MSB address to Y=8 (1000). Each register contains one byte (8-bits) of data corresponding to eight
frames of a particular bit position in timeslot 0. There are 5 registers in total containing 5 bytes of data, occupying
addresses YB0 to YB4. Address YB0 corresponds to bit position 4 (TN0=Sa4) and address YC4 corresponding to
bit position 8 (TN4=Sa8).
Note: For address Y90 (n=0), set all control bits to 0.
Bit
7
6
5
4
3
2
1
0
Table 187 - Timeslot (TS) n (n = 0 to 31) Control Register (Address Y90 (TS0) to YAF(TS31)) (E1)
MPDT(0)
Transmit National Bit RN Data Registers (YB0- YB4) Bit Functions
CASS(n)
RRST(n)
RTSL(n)
TTST(n)
LTSL(n)
TADI(n)
Name
(0)
(0)
(0)
(0)
(0)
(0)
(#)
Channel Associated Signaling (CAS) Source. Selects the source for the CAS data
(A,B,C,D) on the transmit PCM30 link in bit positions one to four, and five to eight of
timeslot 16 in frames 1 to 15. If zero, ST-BUS (CSTi) is selected as the source. If one, data
register (register address Y5,6n) is selected as the source. For n=1 to 15, the CASS(n) bit
corresponds to timeslot n which corresponds to channel n. For n=17 to 31, the CASS(n)
bit corresponds to timeslot n which corresponds to channel n-1.
Transmit Alternate Digit Inversion. If one, the data sourced from DSTi timeslot n (n = 0
to 31) to the transmit PCM30 link timeslot n has every second bit inverted, If zero, this bit
has no effect on channel data.
Remote Timeslot Loopback. If one, the data from the received PCM30 link timeslot n (n
= 0 to 31) is output on DSTo timeslot n and is also looped back to the transmit PCM30 link
timeslot n. If zero, the loopback is disabled.
Local Timeslot Loopback. If one, the data sourced from DSTi timeslot n (n = 0 to 31) to
the transmit PCM30 link timeslot n is also looped back to DSTo timeslot n. If zero, this
loopback is disabled.
Transmit Test. If one and control bit ADSEQ (register address Y01) is one, the A-law
digital milliwatt will be transmitted in PCM30 timeslot n. When one and ADSEQ is zero, a
Pseudo-Random Bit Sequence (PRBS 2
More than one timeslot may be activated at once. If zero, neither of these test signals will
be connected to timeslot n.
Receive Test. If one and control bit ADSEQ (register address Y01) is one, the A-law
digital milliwatt will be transmitted in DSTo timeslot n. When one and ADSEQ is zero, a
Pseudo Random Bit Sequence (PRBS 2
n. This receiver circuit will synchronize to the transmit PRBS signal and perform a bit
comparison of the two sequences. If zero, neither of these test signals will be connected to
the corresponding timeslot.
Micro Port Data Transmit. Setting this bit allows for the transmit data for a given channel
to be replaced by the idle code(Y0A). The idle code can be written by the micro port for
trunck conditioning applications. The data in Y0A will replace the appropriate PCM30
channel.
not used.
Zarlink Semiconductor Inc.
MT9072
212
Functional Description
15
15
-1) receiver will be connected to DSTo timeslot
-1) will be transmitted in PCM30 timeslot n.
Data Sheet