mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 31

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
LQFP
136
156
116
36
56
76
17
97
Pin #
LBGA
M16
G14
C16
T15
G3
L4
T2
T8
CSTo(0)
CSTo[4]
CSTi[1]
CSTi[2]
CSTi[3]
CSTi[5]
CSTi[6]
CSTi[7]
Name
Type
OH Control ST-BUS. This pin is the signaling output for the receive side
I
Control ST-BUS. In 2.048 Mbit/s ST-BUS mode this pin is the
signaling input for the transmit side of the framer. This pin has no
function in 8.192 Mbit/s ST-BUS mode or IMA mode. Pins CSTi[0-7]
are used by Framers[0-7] respectively. The CSTi data stream is
clocked into the framer by the clock input to pin CKi.
In T1 robbed bit signaling mode the first 24 ST-BUS channels contain
(XXXXABCD) signaling nibbles to be transmitted for their respective
DS0s. The least significant nibbles (bits 3-0) are valid and the most
significant nibbles of each channel are ignored.
In T1 CCS (Common Channel Signaling) mode, the CSTi pin can be
connected to the output of an external multi-channel HDLC. Any one
of the framer’s transmit timeslots can be programmed to transmit the
data appearing at the CSTi pin on any one of the first 24 ST-BUS
channels. See the descriptions of the CSIGEN control bit (Address
Y04) and the Common Channel Signaling Map Register (Address
Y0B).
In E1 CAS (Channel Associated Signaling) mode, the 32 ST-BUS
channels contain (XXXXABCD) signaling nibbles to be transmitted for
their respective timeslots. The least significant nibbles (bits 3-0) are
valid and the most significant nibbles of each channel are ignored.
See Table 25.
In E1 CCS (Common Channel Signaling) mode, the CSTi pin can be
connected to the output of an external multi-channel HDLC. The
framer’s transmit timeslots 15, 16 and 31 can each be programmed to
transmit the data appearing at the CSTi pin on any one of the 32
ST-BUS channels. See the descriptions of the CSIG control bit
(Address Y03) and the TS15E, TS16E and TS31E control bits
(Address Y06) and see Table 27.
of the framer. In 2.048 Mbit/s ST-BUS mode it operates the same as
CSTo(1-3), it can also operate in 8.192 Mbit/s ST-BUS mode. The
CSTo data stream is clocked out of the framer by the clock input to pin
CKi. This pin has no function in IMA mode.
When operated in 8.192 Mbit/s ST-BUS mode this pin outputs a data
stream containing 128 8-bit channels accommodating four framers.
See Table 2 and Table 5. The CSTo[0] pin is used by Framers [0-3]
and the CSTo[4] pin is used by Framers [4-7]. The frame boundary is
indicated by the FPi inputs. FPi[0] is used for Framers[0-3] and FPi[4]
is used for Framers[4-7].
The 32 ST-BUS channels mapped to each framer are treated as
described for CSTo(1-3) operating at 2.048 Mbit/s.
Zarlink Semiconductor Inc.
MT9072
31
Description (see Notes 1 to 7)
Data Sheet