mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 265

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

ST-BUS
Bit Cells
2 Mb/s
ST-BUS
Bit Cells
8 Mb/s
FPi
(ST-BUS F0i)
Internal
(ST-BUS C2)
CKi
(ST-BUS C4i)
FPi
(ST-BUS F16i)
CKi
(ST-BUS C16i)
TxDLC - Note 2
(Output)
TxDLC - Note 3
(Output)
TxDL
(Input)
(2Mb/s)
TxDLC - Note 2
(Output)
TxDLC - Note 3
(Output)
Note 1 - TxDLC output applies for every second frame (FPi) pulse (250 us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
76543210
Bit
Bit
TS124
7
7
Bit
Sa4 to Sa8 clocked in by MT9072
Sa4 to Sa8 clocked in by MT9072
Example A - 20 kbit/s clock output
Example A - enable output
Example B - 12 kbit/s clock output
Sa4, Sa7 and Sa8 clocked in by MT9072
Example B - enable output
Sa4, Sa7 and Sa8 clocked in by MT9072
Bit
6
Bit
6
76543210
Figure 66 - Transmit Data Link Pin Functional Timing
Bit
5
Bit
5
TS125
Bit
Timeslot 31
Bit
4
Bit
4
76543210
Bit
3
Bit
3
TS126
Bit
Bit
2
Bit
2
76543210
Zarlink Semiconductor Inc.
Bit
Bit
1
TS127
1
Bit
Bit
Bit
0
0
MT9072
76543210
Bit
Bit
7
265
7
TS0
Bit
Bit
6
Bit
6
76543210
Bit
5
Bit
5
Timeslot 0
TS1
Bit
Bit
Sa4
Bit
4
76543210
Bit
Sa5
Bit
3
Bit
TS2
Bit
Sa6
Bit
2
76543210
Bit
Sa7
Bit
1
Bit
TS3
Bit
Bit
Sa8
0
76543210
Bit
7
Bit
7
Bit
TS4
Timeslot 1
Bit
6
Bit
6
76543210
Bit
5
Bit
5
Bit
TS5
Bit
4
Bit
4
Data Sheet