mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 259

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mt9072av2

Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet

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19.2.1
In both the transmit and receive directions, PCM24 LSB maps to ST-BUS LSB.
‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1. High impedance is measured by pulling to the appropriate rail with R
C
L
.
CHANNEL
31 or 127
FRAME
AC Electrical Characteristics - PCM24 and ST-BUS Frame Format
15
CHANNEL
FRAME
Significant
Bit (First)
Significant
0
0
Bit (First)
Most
Most
timeslot
BIT
0
1
BIT
7
• • • • • • • •
BIT
2
timeslot
• • •
BIT
Figure 55 - PCM 24 Format
Figure 56 - ST-BUS Format
6
Zarlink Semiconductor Inc.
1
BIT
3
MT9072
BIT
2.0 ms
5
125 µs
BIT
(8/2.048) µs
4
259
(8/2.048 or 8/8.192) µs
BIT
• • • •
4
BIT
5
125 µs
L
BIT
, with timing corrected to cancel time taken to discharge
CHANNEL
BIT
3
30 or 126
6
FRAME
14
BIT
BIT
2
7
timeslot
31 or 127
CHANNEL
BIT
30
BIT
8
1
FRAME
15
Least
Significant
Bit (Last)
BIT
0
timeslot
CHANNEL
31
FRAME
Least
Significant
Bit (Last)
0
0
Data Sheet

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