mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 66

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Y-bit is zero; when CAS multiframing is not acquired, the transmit Y-bit is one. Refer to ITU-T G.704 and G.732 for
more details on CAS multiframing requirements. Registers related to configuration and observation of the CAS
signaling are shown in Table 23.
Timeslot 16 of the remaining 15 basic frames of the CAS multiframe (i.e., basic frames 1 to 15) is reserved for the
ABCD signaling bits for the 30 payload channels. The most significant nibbles are reserved for channels 1 to 15 and
the least significant nibbles are reserved for channels 16 to 30. That is, timeslot 16 of basic frame 1 has ABCD for
channel 1 and 16, timeslot 16 of basic frame 2 has ABCD for channel 2 and 17, through to timeslot 16 of basic
frame 15 has ABCD for channel 15 and 30. See Table 24. Note that the ABCD bits for TS1 to TS15 should not be
0000 to prevent mimic of the multiframe alignment signal(0000).
Register
Address
Y51-Y6F Per Channel Transmit
Y90 to
YAF
Y00
Y02
Y03
Y04
Y05
Y06
Y10
Y26
Y36
Y46
900
Global Control 0
Alarm and Framing Control
Register
Interrupt and IO Control
Register
DL,CCS,CAS and other
Control Register
Signaling Interrupt Period
Register
CAS Control and Data
Register
HDLC and CCS ST-BUS
Control Register
Synchronization and CRC-4
Remote Status.
CAS, National, CRC-4 Local
and Timer Latch Status
CAS, national, CRC-4 Local
and Timer Interrupt Status
National Interrupt Mask
Register
Signaling
Per Channel Timeslot
Control Register
Register
Table 23 - Registers Related to CAS Signaling (E1)
CK1 determines an 8.192 Mbits stream or a 2.048 Mbits stream.
STBUS selects a GCI or ST-BUS CSTi, CSTo streams.
Ensure that TAIS16 is off, the signaling information in CAS cannot be
sent if TAIS16 is on. Also signaling is not supported in IMA mode.
If CSTo is to contain the signaling nibbles set CSTOE to 1 and RXCO to
1.
RXTRS which sets the receiver in a transparent mode has to be turned
off.
Bit 0 and 1 of this register determine the period of the interrupt CASRI.
The period is selectable from 2 msec 8 msec and 16 msec.
If RFL is set the receive signaling is frozen due to synchronization loss.
If debounce is selected a 14 msec debounce is applied before the
signaling is available in the csto or receive CAS register.
TS31E, TS15E and TS16E have to be off since Common Channel
signaling and CAS are mutually exclusive.
MSYNC has to be low for the signaling in the Receive CAS Registers
or CSTO has valid data.
The bit CASRL reflects the signaling changes on the receive CAS.
The CASRI will be set if a signaling Interrupt has occurred. The period
of the interrupt is controlled by the signaling Interrupt Period
Register(Y04).
The bit CASRM can be used to mask interrupts from the receive
signaling changes.
The clear channel bit can be used to block insertion of signaling in the
transmit direction. The CASS bit can be used to determine the source
of the transmit signaling, which is either the CSTi or the transmit
signaling ram.
The CASS bit determines the source of the transmit signaling which is
either the ST-BUS or the transmit signaling registers(Y51 to Y60).
Zarlink Semiconductor Inc.
MT9072
66
Description
Data Sheet
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